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Preliminary Technical Data
FEATURES
Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI(R) MCU ADUC7122
Software-triggered in-circuit reprogrammability On-chip peripherals UART, 2 x I2C and SPI serial I/O 32-pin GPIO port 4x general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor Vectored interrupt controller for FIQ and IRQ 8 Priority levels for each interrupt type Interrupt on edge or level external pin inputs Power Specified for 3 V operation Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz Packages and temperature range 7 mm x 7mm 108-ball BGA Fully specified for -10C to +95C operation Tools Low cost QuickStartTM development system Full third-party support
Analog I/O 13 external channel, 12-bit, 1 MSPS ADC 2 channels with programmable gain PGA (1 to 5) input range IOVDD power monitor channel On-chip temperature monitor 11 general-purpose inputs Fully differential and single-ended modes 0 V to VREF analog input range 12 x 12-bit voltage output DACs On-chip voltage reference: 1.2 V/2.5 V Buffered output reference sources for use with external circuits Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (3%) External watch crystal External clock source up to 41.78 MHz 41.78 MHz PLL with programmable divider Memory 126 kB Flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug
APPLICATIONS
Optical networking, industrial control, and automation systems Smart sensors, precision instrumentation, base station systems
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Rev. PrA
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ADUC7122 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Specifications..................................................................................... 3 Timing Specifications .................................................................. 7 Absolute Maximum Ratings.......................................................... 12 ESD Caution ................................................................................ 12 Pin Configuration and Function Descriptions ........................... 13 Terminology .................................................................................... 17 ADC Specifications .................................................................... 17 DAC Specifications..................................................................... 17 Overview of the ARM7TDMI Core ............................................. 18 Thumb Mode (T)........................................................................ 18 Long Multiply (M) ...................................................................... 18 EmbeddedICE (I) ....................................................................... 18 Exceptions ................................................................................... 18 ARM Registers ............................................................................ 18 Interrupt Latency ........................................................................ 19 Memory Organization ................................................................... 20 Flash/EE Memory ....................................................................... 20 SRAM ........................................................................................... 20 Memory Mapped Registers ....................................................... 20 Complete MMR Listing ............................................................. 21 ADC Circuit Overview .................................................................. 25 ADC Transfer Function ............................................................. 26 Typical Operation ....................................................................... 27 Temperature Sensor ................................................................... 28 Converter Operation .................................................................. 31 Driving the Analog Inputs ........................................................ 32 Band Gap Reference ................................................................... 33 Power Supply Monitor ............................................................... 33 Nonvolatile Flash/EE Memory ..................................................... 34 Flash/EE Memory Overview..................................................... 34 Flash/EE Memory ....................................................................... 34 Flash/EE Memory Security ....................................................... 35 Flash/EE Control Interface........................................................ 35 Execution Time from SRAM and FLASH/EE ........................ 38 Reset and Remap ........................................................................ 39 Other Analog Peripherals .............................................................. 40
2
Preliminary Technical Data
DAC.............................................................................................. 40 LDO (Low Dropout Regulator) ................................................ 42 Oscillator and PLL--Power Control ............................................ 43 External Crystal Selection ......................................................... 43 External Clock Selection ........................................................... 43 Power Control System ............................................................... 44 MMRs and Keys ......................................................................... 45 Digital Peripherals .......................................................................... 46 PWM General Overview ........................................................... 46 PWM Convert Start Control .................................................... 48 General-Purpose I/O ..................................................................... 49 UART Serial Interface .................................................................... 52 Baud Rate Generation ................................................................ 52 UART Register Definition ......................................................... 52 I C ..................................................................................................... 57 Serial Clock Generation ............................................................ 57 I2C Bus Addresses ....................................................................... 57 I2C Registers ................................................................................ 58 I2C Common registers ............................................................... 66 Serial Peripheral Interface ............................................................. 67 SPIMISO (Master In, Slave Out) Pin ....................................... 67 SPIMOSI (Master Out, Slave In) Pin ....................................... 67 SPICLk (Serial Clock I/O) Pin ................................................. 67 SPI Chip Select (SPI CS Input) Pin .......................................... 67 Configuring External pins for SPI functionality .................... 67 SPI Registers ................................................................................ 68 Programmable Logic Array (PLA) ............................................... 71 Interrupt System ......................................................................... 73 IRQ ............................................................................................... 74 Fast Interrupt Request (FIQ) .................................................... 74 Timers .......................................................................................... 80 Timer0--Lifetime Timer ........................................................... 80 Timer1--General-Purpose Timer ........................................... 82 Timer2--Wake-Up Timer ......................................................... 84 Timer3--Watchdog Timer ........................................................ 86 Timer4--General-Purpose Timer ........................................... 88 Outline Dimensions ....................................................................... 90 Ordering Guide .......................................................................... 90
Rev. PrA | Page 2 of 92
Preliminary Technical Data SPECIFICATIONS
ADUC7122
AVDD = IOVDD = 3.0 V to 3.6 V, 5%, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = -10C to +95C, unless otherwise noted. Table 1.
Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy1, 2 Resolution Integral Nonlinearity Differential Nonlinearity3, 4 DC Code Distribution ENDPOINT ERRORS5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode Single-Ended Mode Leakage Current Input Capacitance Input Capacitance PADC0 Input Full Scale Input Range Input Leakage at PADC0P4 Resolution Gain Error4 Gain Drift4 Offset4 Offset Drift4 PADC0P Compliant Range PADC1 Input Full Scale Input Range Input Leakage at PADC1P4 Resolution Gain Error4 Gain Drift4 Offset4 Offset Drift4 PADC1P Compliant Range ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy7 Reference Temperature Coefficient4 Min Typ 5 12 0.6 0.5 1 2 1 2 1 2 +1..4/-0.99 Max Unit s Bits LSB LSB LSB LSB LSB LSB LSB fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS internally unbuffered channels Includes distortion and noise components Test Conditions/Comments Eight acquisition clocks and fADC/2
2.5 V internal reference, not production tested for PADC0/PADC1 channels 2.5 V internal reference, gauranteed monotonic ADC input is a dc voltage Internally unbuffered channels
5 5
69 -78 -75 -80
dB dB dB dB
Measured on adjacent channels
0.15 0.2 20 20 20 0.15 11
VCM6 VREF/2 0 to VREF AVdd-1.5
V V V A pF pF A nA Bits % ppm/C nA pA/C V A nA Bits % ppm/C nA pA/C V V mV ppm/C
See Table 35 and Table 36 Buffer bypassed Buffer enabled During ADC acquisition buffer bypassed During ADC acquisition buffer enabled 28.3 k resistor, PGA gain = 3
1000 2 1 50 6 60 AVdd-1.2 700 2 1 50 6 60 AVdd-1.2
0.1% accuracy, 5 ppm external resistor for I to V
3 30 0.1 10.6 0.15 11
PGA offset not included
53.5 k resistor, PGA gain = 3
0.1% accuracy, 5 ppm external resistor for I to V
3 30 0.1 2.5 10
PGA offset not included
0.47 F from VREF to AGND 5 30 TA = 25C
Rev. PrA | Page 3 of 92
ADUC7122
Parameter Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT Input Voltage Range External reference input Leakage current DAC CHANNEL SPECIFICATIONS DC Accuracy8 Resolution Relative Accuracy Differential Nonlinearity Calculated Offset Error Actual Offset Error Gain Error9 Gain Error Mismatch Settling Time PSRR4 DC 1kHz 10 kHz 100 kHz OFFSET DRIFT4 GAIN ERROR DRIFT4 SHORT CIRCUIT CURRENT ANALOG OUTPUTS Output Range DAC AC CHARACTERISTICS Slew Rate Voltage Output Settling Time Digital-to-Analog Glitch Energy Min Typ 61 10 1 Max Unit dB ms V A
Preliminary Technical Data
Test Conditions/Comments TA = 25C
1.2
AVDD TBD
RL = 5 k, CL = 100 pF Buffered 12 2 0.2 2 9 0.15 0.1 10 -59 -57 -47 -19 -61 Bits LSB LSB mV mV % % s dB dB dB dB V/C V/C mA Buffer on
1
Guaranteed monotonic 2.5 V internal reference Measured at Code 0 % of full scale on DAC0 Buffered
0.8
10 10 20 0.1 VREF/AVDD - 0.1 2.49 10 20
V/s s nV-sec
1 LSB change at major carry (where maximum number of bits simultaneously change in the DACxDAT register)
TEMPERATURE SENSOR10 Voltage Output at 25C Voltage TC Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy POWER-ON RESET WATCHDOG TIMER (WDT) Timeout Period FLASH/EE MEMORY Endurance11 Data Retention12 DIGITAL INPUTS Logic 1 Input Current Logic 0 Input Current Input Capacitance
707 -1.25 3
mV mV/C C
MCU in power-down or standby mode before measurement Two selectable trip points Of the selected nominal trip point voltage
2.79 3.07 2.5 2.36 0 10,000 20 0.2 -40 10 1 -60 512
V V % V sec cycles years A A pF
TJ = 85C All digital inputs excluding XCLKI and XTALO VIH = VDD or VIH = 5 V VIL = 0 V; except TDI
Rev. PrA | Page 4 of 92
Preliminary Technical Data
Parameter LOGIC INPUTS4 VINL, Input Low Voltage4 VINH, Input High Voltage4 LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage13 CRYSTAL INPUTS XTALI and XTALO Logic Inputs, XTALI Only VINL, Input Low Voltage VINH, Input High Voltage XTALI Input Capacitance XTALO Output Capacitance INTERNAL OSCILLATOR MCU CLOCK RATE From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element Propagation Delay POWER REQUIREMENTS14, 15 Power Supply Voltage Range AVDD to AGND and IOVDD to IOGND Analog Power Supply Currents AVDD Current Digital Power Supply Current IOVDD Current in Normal Mode Min Typ Max 0.8 2.0 2.4 0.4 Unit V V V V Test Conditions/Comments All logic inputs excluding XTALI
ADUC7122
All digital outputs excluding XTALO ISOURCE = 1.6 mA ISINK = 1.6 mA
1.1 1.7 20 20 32.768 3 326 41.78 0.05 70 24 3.06 1.58 1.7 12 2.5 41.78
V V pF pF kHz % kHz MHz MHz ms ns s ms ms ns ns CD = 7 CD = 0 TA = 95C Core clock = 41.78 MHz CD = 0 CD = 7
From input pin to output pin
2.7 200
3.6
V A ADC in idle mode Code executing from Flash/EE CD = 7 CD = 3 CD = 0 (41.78 MHz clock) CD = 0 (41.78 MHz clock) TA = 85C At 1 MSPS At 62.5 kSPS Per DAC
IOVDD Current in Pause Mode4 IOVDD Current in Sleep Mode4 Additional Power Supply Currents ADC DAC
7 11 30 25 100 2.7 0.7 250
40
mA mA mA mA A mA mA A
Rev. PrA | Page 5 of 92
ADUC7122
Parameter ESD TESTS HBM Passed Up to FCIDM Passed Up to
1 2 3
Preliminary Technical Data
Min Typ Max 4 0.5 Unit kV kV Test Conditions/Comments 2.5 V reference, TA = 25C
All ADC channel specifications are guaranteed during normal MicroConverter core operation. Apply to all ADC input channels. Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN); see the the Calibration section. 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 22. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the ADC Circuit Overview). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 VREF calibration and trimming are performed with core operating in normal mode CD = 0, ADC on, and all DACs on. VREF accuracy may vary under other operating conditions. 8 DAC linearity is calculated using a reduced code range of 100 to 3995. 9 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 10 Die temperature. 11 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at -40C, +25C, +85C, and +125C. 12 Retention lifetime equivalent at junction temperature (TJ) = 85C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 13 Test carried out with a maximum of eight I/Os set to a low output level. 14 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with 3.6 V supply, and sleep mode with 3.6 V supply. 15 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
Rev. PrA | Page 6 of 92
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 2. I2C Timing in Fast Mode (400 kHz)
Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCLOCK low pulse width SCLOCK high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCLx and SDAx Fall time for both SCLx and SDAx Min 200 100 300 100 0 100 100 1.3 Slave Max
ADUC7122
Master Typ 1360 1140 740 400 800
300 300
200
Unit ns ns ns ns ns ns ns s ns ns
Table 3. I2C Timing in Standard Mode (100 kHz)
Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCLOCK low pulse width SCLOCK high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCLx and SDAx Fall time for both SCLx and SDAx
tBUF
SDATA (I/O)
Min 4.7 4.0 4.0 250 0 4.7 4.0 4.7
Slave Max
3.45
1 300
Unit s ns s ns s s s s s ns
tSUP tR
MSB LSB ACK MSB
tDSU tPSU tSHD
SCLK (I) P S 1 2-7
tDHD tH
8
tDSU tRSU
9
tF tDHD tR
1 S(R) REPEATED START
STOP START CONDITION CONDITION
Figure 2. I2C-Compatible Interface Timing
Rev. PrA | Page 7 of 92
04955-054
tL
tSUP
tF
ADUC7122
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF
1
Preliminary Technical Data
Description SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Min Typ (SPIDIV + 1) x tUCLK (SPIDIV + 1) x tUCLK Max Unit ns ns ns ns ns ns ns ns ns
25 1 x tUCLK 2 x tUCLK 5 5 5 5 12.5 12.5 12.5 12.5
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1)
tSH tSL tSR tSF
tDAV
MOSI MSB
tDF
tDR
BITS 6 TO 1 LSB
MISO
MSB IN
BITS 6 TO 1
LSB IN
04955-055
tDSU tDHD
Figure 3. SPI Master Mode Timing (PHASE Mode = 1)
Rev. PrA | Page 8 of 92
Preliminary Technical Data
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF
1
ADUC7122
Min Typ (SPIDIV + 1) x tUCLK (SPIDIV + 1) x tUCLK Max Unit ns ns ns ns ns ns ns ns ns ns
Description SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
25 75 1 x tUCLK 2 x tUCLK 5 5 5 5 12.5 12.5 12.5 12.5
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK (POLARITY = 0)
tSH tSL tSR
SCLOCK (POLARITY = 1)
tSF
tDOSU
MOSI MSB
tDAV tDF tDR
BITS 6 TO 1 LSB
MISO
MSB IN
BITS 6 TO 1
LSB IN
tDHD
Figure 4. SPI Master Mode Timing (PHASE Mode = 0)
Rev. PrA | Page 9 of 92
04955-056
tDSU
ADUC7122
Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS
1
Preliminary Technical Data
Description CS to SCLOCK edge SCLOCK low pulse width1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge Min 200 Typ (SPIDIV + 1) x tUCLK (SPIDIV + 1) x tUCLK 25 1 x tUCLK 2 x tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5 Max Unit ns ns ns ns ns ns ns ns ns ns ns
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH tSL tSR
SCLOCK (POLARITY = 1)
tSF
tDAV
MISO MSB
tDF
tDR
BITS 6 TO 1 LSB
MOSI
MSB IN
BITS 6 TO 1
LSB IN
04955-057
tDSU tDHD
Figure 5. SPI Slave Mode Timing (PHASE Mode = 1)
Rev. PrA | Page 10 of 92
Preliminary Technical Data
Table 7. SPI Slave Mode Timing (Phase Mode = 0)
Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS
1
ADUC7122
Min 200 Typ (SPIDIV + 1) x tUCLK (SPIDIV + 1) x tUCLK 25 1 x tUCLK 2 x tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5 25 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
Description CS to SCLOCK edge SCLOCK low pulse width1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH
SCLOCK (POLARITY = 1)
tSL tSR tSF
tDAV tDOCS tDF
MISO MSB
tDR
BITS 6 TO 1 LSB
MOSI
MSB IN
BITS 6 TO 1
LSB IN
04955-058
tDSU tDHD
Figure 6. SPI Slave Mode Timing (PHASE Mode = 0)
Rev. PrA | Page 11 of 92
ADUC7122 ABSOLUTE MAXIMUM RATINGS
AGND = REFGND = DACGND = GNDREF, TA = 25C, unless otherwise noted. Table 8.
Parameter AVDD to IOVDD AGND to DGND IOVDD to IOGND, AVDD to AGND Digital Input Voltage to IOGND Digital Output Voltage to IOGND VREF_2.5 and VREF_1.2 to AGND Analog Inputs to AGND Analog Outputs to AGND Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature JA Thermal Impedance 108-Ball CSP_BGA Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) RoHS-Compliant Assemblies (20 sec to 40 sec) Rating -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +6 V -0.3 V to +5.3 V -0.3 V to IOVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -40C to +125C -65C to +150C 150C 40C/W 240C 260C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Rev. PrA | Page 12 of 92
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 11 10 9 8 7 6 5 4 3 2 1 A1 corner A B C
ADUC7122
n.c. n.c. /RST
n.c. n.c. P3.1
n.c. AGND TDI/ P1.2 TDO/ P1.3 TMS TCK P0_7 P2.4 P2.5 DAC9
n.c. AGND P2.7
n.c. n.c. n.c.
n.c.
n.c.
n.c. n.c. n.c.
n.c. n.c. P3.0
n.c. P1.6 P0.2
n.c. P1.7 P1.0
n.c. n.c. P2.6
REG_PWR AGND n.c. n.c.
P3.6
P0.0
P0.3
P1.1
P3.2
D
P3.7 DGND LVDD IOVDD IOGND DAC11
P0.1 P2.0 P2.1 P2.2 P2.3 DAC10
P0.4 P0.5 P0.6 P1.4 P1.5 ADC9 ADC10/ AINCM BUF_ VREF2 PADC1P BUF_ VREF1 PADC0P Vref_1.2 AGND ADC3 DAC5 ADC5 ADC0 ADC1 ADC4
P3.4 P3.5 XTALO XTALI DAC2 DAC1
P3.3 DGND LVDD IOVDD IOGND DAC0
E F G H J K
AVDD AGND
DAC7 DAC6
DAC8 ADC6
ADC8 AIN7
Vref_2.5
DAC3 DAC4
AVDD AGND
L M
PADC1N AVDD
PADC0N ADC2
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. C12 D11 Mnemonic RST P0.0/SCL1/PLAI[5] Type1 I I/O Description Reset Input (Active Low). General-Purpose Input and Output Port 0.0 (P0.0). I2C Interface SCLOCK for I2C0 (SCL1). Input to PLA Element 5 (PLAI[5]). General-Purpose Input and Output Port 0.1 (P0.1). I2C Interface SDATA for I2C0 (SDA1). Input to PLA Element 4 (PLAI[4]). General-Purpose Input and Output Port 0.2 (P0.2). SPI Clock (SPICLK). Output of PLA Element 13 (PLAO[13]). General-Purpose Input and Output Port 0.3 (P0.3). SPI Master Input, Slave Output (SPIMISO). Output of PLA Element 12 (PLAO[12]). TBD (SYNC). General-Purpose Input and Output Port 0.4 (P0.4). SPI Master Out Slave Input (SPIMOSI). Input to PLA Element 11 (PLAI[11]). TBD (TRIP).
Rev. PrA | Page 13 of 92
E11
P0.1/SDA1/PLAI[4]
I/O
C3
P0.2/SPICLK/PLAO[13]
I/O
D3
P0.3/SPIMISO/PLAO[12]/SYNC
I/O
E3
P0.4/SPIMOSI/PLAI[11]/TRIP
I/O
ADUC7122
Pin No. F3 Mnemonic P0.5/SPICS/PLAI[10]/CONVST Type1 I/O
Preliminary Technical Data
Description General-Purpose Input and Output Port 0.5 (P0.5). SPI Slave Select Input (SPICS). Input to PLA Element 10 (PLAI[10]). TBD (CONVST). General-Purpose Input and Output Port 0.6 (P0.6). Power-On Reset Output (MRST). Input to PLA Element 2 (PLAI[2]) General-Purpose Input and Output Port 0.7 (P0.7). JTAG Test Port Input, Test Reset (TRST). Debug and download access. Input to PLA Element 3 (PLAI[3]). General-Purpose Input and Output Port 1.0 (P1.0). Serial Input, Receive Data (RxD), UART (SIN) I2C Interface SCLOCK for I2C1 (SCL2). Input to PLA Element 7 (PLAI[7]). General-Purpose Input and Output Port 1.1 (P1.1). Serial Output, Transmit Data (TxD), UART (SOUT) I2C Interface SDATA for I2C1 (SDA2). Input to PLA Element 6 (PLAI[6]). General-Purpose Input and Output Port 1.4 (P1.4). PWM1 Output (PWM1). Input to PLA Element 8 (PLAI[8]). General-Purpose Input and Output Port 1.5 (P1.5). PWM2 Output (PWM2). Input to PLA Element 9 (PLAI[9]). General-Purpose Input and Output Port 1.6 (P1.6). Output of PLA Element 5 (PLAO[5]). General-Purpose Input and Output Port 1.7 (P1.7). Output of PLA Element 4 (PLAO[4]). General-Purpose Input and Output Port 2.0 (P2.0). External Interrupt Request 0 (IRQ0). Input to PLA Element 13 (PLAI[13]). General-Purpose Input and Output Port 2.1 (P2.1). External Interrupt Request 1 (IRQ0). Input to PLA Element 12 (PLAI[12]). General-Purpose Input and Output Port 2.2 (P2.2). Input to PLA Element 1 (PLAI[1]). General-Purpose Input and Output Port 2.3 (P2.3). External Interrupt Request 2 (IRQ2). Input to PLA Element 14 (PLAI[14]). General-Purpose Input and Output Port 2.4 (P2.4). PWM5 Output (PWM5). Output of PLA Element 7 (PLAO[7]). General-Purpose Input and Output Port 2.5 (P2.5). PWM6 Output (PWM6). Output of PLA Element 6 (PLAO[6]). General-Purpose Input and Output Port 2.6 (P2.6). External Interrupt Request 3 (IRQ3). Input to PLA Element 15 (PLAI[15]). General-Purpose Input and Output Port 2.7 (P2.7). Input to PLA Element 0 (PLAI[0]). General-Purpose Input and Output Port 3.0 (P3.0). Output of PLA Element 0 (PLAO[0]). General-Purpose Input and Output Port 3.1 (P3.1). Output of PLA Element 1 (PLAO[1]). General-Purpose Input and Output Port 3.2 (P3.2). External Interrupt Request 4 (IRQ4).
Rev. PrA | Page 14 of 92
G3
P0.6/MRST/PLAI[2]
I/O
G10
P0.7/TRST/PLAI[3]
I/O
C2
P1.0/SIN/SCL2/PLAI[7]
I/O
D2
P1.1/SOUT/SDA2/PLAI[6]
I/O
H3
P1.4/PWM1/PLAI[8]/XCLK
I/O
J3
P1.5/PWM2/PLAI[9]
I/O
B3 B2 F11
P1.6/PLAO[5] P1.7/PLAO[4] P2.0/IRQ0/PLAI[13]
I/O I/O I/O
G11
P2.1/IRQ1/PLAI[12]
I/O
H11 J11
P2.2/PLAI[1] P2.3/IRQ2/PLAI[14]
I/O I/O
H10
P2.4/PWM5/PLAO[7]
I/O
J10
P2.5/PWM6/PLAO[6]
I/O
C1
P2.6/IRQ3/PLAI[15]
I/O
C9 C4 C11 D1
P2.7/PLAI[0] P3.0/PLAO[0] P3.1/PLAO[1] P3.2/IRQ4/PWM3/PLAO[2]
I/O I/O I/O I/O
Preliminary Technical Data
Pin No. Mnemonic Type1
ADUC7122
Description PWM3 Output (PWM3). Output of PLA Element 2 (PLAO[2]). General-Purpose Input and Output Port 3.3 (P3.3). External Interrupt Request 5 (IRQ5). PWM4 Output (PWM4). Output of PLA Element 3 (PLAO[3]). General-Purpose Input and Output Port 3.4 (P3.4). Output of PLA Element 8 (PLAO[8]). General-Purpose Input and Output Port 3.5 (P3.5). Output of PLA Element 9 (PLAO[9]). General-Purpose Input and Output Port 3.6 (P3.6). Output of PLA Element 10 (PLAO[10]). General-Purpose Input and Output Port 3.7 (P3.7). Output of PLA Element 11 (PLAO[11]). Boot Mode (BM). If this pin is low and Address 0x00014 of flash is 0xFFFFFFFF, then the part enters I2C download after the next rest sequence. 2.5 V Reference Output, External 2.5 V Reference Input. Can be used to drive the anode of a photo diode 1.2 V Reference Output, External 1.2 V Reference Input. Cannot be used to source current externally. No connect. Buffered 2.5 V Bias. Maximum load = 1.2 mA. Buffered 2.5 V. Maximum load = 1.2 mA. PADC0 Positive Input Channel. PGA-based ADC input channel. PADC0 Negative Input Channel. PGA-based ADC input channel. PADC1 Positive Input Channel. PGA-based ADC input channel. PADC1 Negative Input Channel. PGA-based ADC input channel. Single-Ended or Differential Analog Input 0/Thermistor Positive Input 0. Single-Ended or Differential Analog Input 1/Thermistor Ground Input 0 Single-Ended or Differential Analog Input 2/Thermistor Positive Input 1. Single-Ended or Differential Analog Input 3/Thermistor Ground Input 1. Single-Ended Analog Input 4/Positive Differential Input 0. Single-Ended Analog Input 5/Negative Differential Input 0. Single-Ended Analog Input 6/Positive Differential Input 1. Single-Ended Analog Input 7/Negative Differential Input 1. Single-Ended Analog Input 8/Positive Differential Input 2. Single-Ended Analog Input 9/Negative Differential Input 2. Single-Ended or Differential Analog Input 10 (ADC10). Common Mode for Pseudo Differential Input (AINCM). 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. 12-Bit DAC Output. No connect. No connect. No connect.
Rev. PrA | Page 15 of 92
E1
P3.3/IRQ5/PWM4/PLAO[3]
I/O
E2 F2 D12 E12
P3.4/PLAO[8] P3.5/PLAO[9] P3.6/PLAO[10] P3.7/PLAO[11]/BM
I/O I/O I/O I/O
L8 L5 B8 K6 K7 L6 M5 L7 M8 K5 K4 M4 L4 K3 M3 M10 M9 L9 K9 K8 K1 K2 J2 L2 M2 L3 M11 L11 L10 K10 K11 K12 B5 C6 A6
VREF_2.5 VREF_1.2 NC BUF_VREF1 BUF_VREF2 PADC0P PADC0N PADC1P PADC1N ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 DAC9 DAC10 DAC11 NC NC NC
AI/O AI/O NC AO AO AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AO AO AO AO AO AO AO AO AO AO AO AO NC NC NC
ADUC7122
Pin No. A8 A7 C8 A5 C5 B4 A4 A1 A3 A2 B1 A12 A9 A11 A10 B12 B11 B10 B9 M1 M6 L1 M7 M12 B6 L12 C7 B7 G1 G12 F1 F12 H1 J1 H12 J12 G2 H2 Mnemonic NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC AGND AGND AGND AGND AVDD AVDD AGND AGND AVDD NC REG_PWR LVDD LVDD DGND DGND IOVDD IOGND IOVDD IOGND XTALO XTALI Type1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC S S S S S S S S S NC S S S S S S S S S DO DI
Preliminary Technical Data
Description No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. No connect. Analog Ground. Analog Ground. Analog Ground. Analog Ground. Analog Supply (3.3 V). Analog Supply (3.3 V). Analog Ground. Analog Ground. Analog Supply (3.3 V). No connect. Output of 2.5 V on-chip Regulator. A 470 nF capacitor to DGND must be connected to this pin. Output of 2.6 V on-chip LDO regulator. A 470 nF capacitor to DGND must be connected to this pin. Output of 2.6 V on-chip LDO regulator. A 470 nF capacitor to DGND must be connected to this pin. Digital ground. Digital ground. 3.3V GPIO Supply. 3.3V GPIO Ground. 3.3V GPIO Supply. 3.3V GPIO Ground. Output from the Crystal Oscillator Inverter. If an external crystal is not being used, this pin can be left unconnected. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. If an external crystal is not being used, this pin should be connected to the DGND system ground. JTAG Test Port Output, Test Data Out (TDO). Debug and download access. General-Purpose Input and Output Port 1.3 (P1.3). JTAG Test Port Input, Test Data In (TDI). Debug and download access. General-Purpose Input and Output Port 1.2 (P1.2). JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Input, Test Mode Select. Debug and download access.
D10 C10 F10 E10
1
TDO/P1.3/PLAO[14] TDI/P1.2/PLAO[15] TCK TMS
DO DI DI DI
I = input, I/O = input/output, AI/O = analog input/output, NC = no connect, AO = analog output, AI = analog input, DI = digital input, DO = digital output, S = supply.
Rev. PrA | Page 16 of 92
Preliminary Technical Data TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000...000) to (0000...001) from the ideal, that is, 1/2 LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale - 1.5 LSB) after the offset error has been adjusted out. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc.
ADUC7122
The ratio is dependent upon the number of quantization levels in the digitization process; the more levels there are, the smaller the quantization noise becomes. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS
Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes the output to settle to within a 1 LSB level for a full-scale input change.
Rev. PrA | Page 17 of 92
ADUC7122 OVERVIEW OF THE ARM7TDMI CORE
The ARM7(R) core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be eight bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with four additional features: T support for the thumb (16-bit) instruction set D support for debug M support for long multiplications I includes the EmbeddedICE module to support embedded system debugging
Preliminary Technical Data
EXCEPTIONS
ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are: Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfers or communication channels with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system.
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16 bits, called the thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the thumb mode has two limitations: Thumb code typically requires more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of time-critical code. The thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling.

Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15) and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in Figure 8. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means the interrupt processing can begin without the need to save or restore these registers, and thus save critical time in the interrupt handling process.
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND USABLE IN USER MODE SYSTEM MODES ONLY
See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM thumb instruction sets.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with a 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result. These results are achieved in fewer cycles than required on a standard ARM7 core.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters a debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE, SRAM, and memory mapped registers.
CPSR
SPSR_FIQ FIQ MODE
SPSR_SVC SVC MODE
SPSR_ABT
USER MODE
ABORT MODE
IRQ MODE
UNDEFINED MODE
Figure 8. Register Organization
Rev. PrA | Page 18 of 92
04955-007
Preliminary Technical Data
More information relative to the programmer's model and the ARM7TDMI core architecture can be found in the following materials from ARM: DDI 0029G, ARM7TDMI Technical Reference Manual DDI 0100, ARM Architecture Reference Manual
ADUC7122
At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 s in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar, but must allow for the fact that FIQ has higher priority and can delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in thumb mode where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.
INTERRUPT LATENCY
The worst-case latency for a fast interrupt request (FIQ) consists of the following: The longest time the request can take to pass through the synchronizer The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC The time for the data abort entry The time for FIQ entry

Rev. PrA | Page 19 of 92
ADUC7122 MEMORY ORGANIZATION
The ADUC7122 incorporates three separate blocks of memory: 8 kB of SRAM and two 64 kB of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the factoryconfigured boot page. These two blocks are mapped as shown in Figure 9. Note that by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000. It is possible to remap the SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. This remap function is described in more detail in the Flash/EE memory chapter.
0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x0009F800 FLASH/EE 0x00080000 RESERVED 0x00041FFF SRAM 0x00040000 RESERVED 0x0001FFFF
06020-025
Preliminary Technical Data
FLASH/EE MEMORY
The 128 kB of Flash/EE are organized as two banks of 32 k x 16 bits. In the upper memory block, 31 k x 16 bits are user space and 1 k x 16 bits is reserved for the factory-configured boot page. The page size of this Flash/EE memory is 512 bytes. The lower 64 kB memory block is organized in a similar manner. It is arranged in 32 k x 16 bits. All of this is available as user space. The 126 kB of Flash/EE are available to the user as code and non-volatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. Therefore, it is recommended that Thumb mode be used when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz in full ARM mode (see the Execution Time from SRAM and FLASH/EE section).
SRAM
The 8 kB of SRAM are available to the user, organized as 2 k x 32 bits, that is, 2 k words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array (see the Execution Time from SRAM and FLASH/EE section).
REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) 0x00000000
Figure 9. Physical Memory Map
Memory Access
The ARM7 core sees memory as a linear array of 232 byte location where the different blocks of memory are mapped as outlined in Figure 9. The ADUC7122 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address.
BIT 31 BYTE 3 . . . B 7 3 BYTE 2 . . . A 6 2 32 BITS BYTE 1 . . . 9 5 1 BIT 0 BYTE 0 . . . 8 4 0 0x00000004
06020-026
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 11 are unoccupied or reserved locations and should not be accessed by user software. Table 10 to Table 26 show a full MMR memory map. The access time reading or writing a MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA buses: advanced high performance bus (AHB) used for system modules, and advanced peripheral bus (APB) used for lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADUC7122 are on the APB except the Flash/EE memory and the GPIOs.
0xFFFFFFFF
0x00000000
Figure 10. Little Endian Format
Rev. PrA | Page 20 of 92
Preliminary Technical Data
Table 10. IRQ Base Address = 0xFFFF0000
Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0100 0x0104 0x0108 0x010C 0x011C 0x013C Name IRQSTA IRQSIG IRQEN IRQCLR SWICFG IRQBASE IRQVEC IRQP0 IRQP1 IRQP2 IRQP3 IRQCONN IRQCONE IRQCLRE IRQSTAN FIQSTA FIQSIG FIQEN FIQCLR FIQVEC FIQSTAN Byte 4 4 4 4 4 4 4 4 4 4 4 1 1 1 1 4 4 4 4 4 1
ADUC7122
Access Type R R R/W W W R/W R R/W R/W R/W R/W R/W R/W W R/W R R R/W W R R/W Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 11. System Control Base Address = 0xFFFF0200
Address 0x0220 0x0230 0x0234 Name REMAP RSTSTA RSTCLR Byte 1 1 1 Access Type R/W R W Cycle 1 1 1
Figure 11. Memory Mapped Registers
COMPLETE MMR LISTING
Note that the Access Type column corresponds to the access time reading or writing an MMR. It depends on the AMBA bus used to access the peripheral. The processor has two AMBA buses: the AHB (advanced high performance bus) used for system modules and the APB (advanced Peripheral bus) used for lower performance peripherals.
Rev. PrA | Page 21 of 92
ADUC7122
Table 12. Timer Base Address = 0xFFFF0300
Address 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 0x038C 0x0390 Name T0LD T0VAL0 T0VAL1 T0CON T0CLRI T0CAP T1LD T1VAL T1CON T1CLRI T1CAP T2LD T2VAL T2CON T2CLRI T3LD T3VAL T3CON T3CLRI T4LD T4VAL T4CON T4CLRI T4CAP Byte 2 2 4 4 1 2 4 4 4 1 4 4 4 4 1 2 2 2 1 4 4 4 1 4 Access Type R/W R R R/W W R R/W R R/W W R R/W R R/W W R/W R R/W W R/W R R/W W R Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Address 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0520
Preliminary Technical Data
Table 16. ADC Base Address = 0xFFFF0500
Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST PGA_GN Byte 4 1 1 1 4 1 2 Access Type R/W R/W R/W R R W R/W Cycle 2 2 2 2 2 2 2
Table 17. DAC Base Address = 0xFFFF0580
Address 0x0580 0x0584 0x0588 0x058C 0x0590 0x0594 0x0598 0x059C 0x05A0 0x05A4 0x05A8 0x05AC 0x05B0 0x05B4 0x05B8 0x05BC 0x05C0 0x05C4 0x05C8 0x05CC 0x05D0 0x05D4 0x05D8 0x05DC Name DAC0CON DAC0DAT DAC1CON DAC1DAT DAC2CON DAC2DAT DAC3CON DAC3DAT DAC4CON DAC4DAT DAC5CON DAC5DAT DAC6CON DAC6DAT DAC7CON DAC7DAT DAC8CON DAC8DAT DAC9CON DAC9DAT DAC10CON DAC10DAT DAC11CON DAC11DAT Byte 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Table 13. PLL Base Address = 0xFFFF0400
Address 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 Name POWKEY1 POWCON POWKEY2 PLLKEY1 PLLCON PLLKEY2 Byte 2 1 2 2 1 2 Access Type W R/W W W R/W W Cycle 2 2 2 2 2 2
Table 14. PSM Base Address = 0xFFFF0440
Address 0x0440 Name PSMCON Byte 2 Access Type R/W Cycle 2
Table 15. Reference Base Address = 0xFFFF0480
Address 0x0480 Name REFCON Byte 1 Access Type R/W Cycle 2
Rev. PrA | Page 22 of 92
Preliminary Technical Data
Table 18. UART0 Base Address = 0xFFFF0800
Address 0x0800 Name COM0TX COM0RX COMDIV0 COMIEN0 COMDIV1 COMIID0
COMCON0 COMCON1 COMSTA0 COMSTA1
ADUC7122
Table 20. I2C1 Base Address = 0xFFFF0900
Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Address 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0920 0x0924 0x0928 0x092C 0x0930 0x0934 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C Name I2C1MCTL I2C1MSTA I2C1MRX I2C1MTX I2C1MRCNT I2C1MCRCNT I2C1ADR0 I2C1ADR1 I2C1SBYTE I2C1DIV I2C1SCTL I2C1SSTA I2C1SRX I2C1STX I2C1ALT I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1FSTA Byte 2 2 1 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 Access Type R/W R R R/W R/W R R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0820 0x0824 0x0828 0X082C
COMSCR COMIEN1 COMIID1 COMADR COMDIV2
Byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
Access Type R/W R R/W R/W R/W R R/W R/W R R R/W R/W R R/W R/W
Table 19. I2C0 Base Address = 0xFFFF0880
Address 0x0880 0x0884 0x0888 0x088C 0x0890 0x0894 0x0898 0x089C 0x08A0 0x08A4 0x08A8 0x08AC 0x08B0 0x08B4 0x08B8 0x08BC 0x08C0 0x08C4 0x08C8 0x08CC Name I2C0MCTL I2C0MSTA I2C0MRX I2C0MTX I2C0MRCNT I2C0MCRCNT I2C0ADR1 I2C0ADR2 I2C0SBYTE I2C0DIV I2C0SCTL I2C0SSTA I2C0SRX I2C0STX I2C0ALT I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0FSTA Byte 2 2 1 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 Access Type R/W R R R/W R/W R R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Table 21. SPI Base Address = 0xFFFF0A00
Address 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 Name SPISTA SPIRX SPITX SPIDIV SPICON Byte 1 1 1 1 2 Access Type R R W R/W R/W Cycle 2 2 2 2 2
Rev. PrA | Page 23 of 92
ADUC7122
Table 22. PLA Base Address = 0xFFFF0B00
Address 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLAOUT Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 4 4 4 4 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Address 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20
Preliminary Technical Data
Table 24. Flash/EE Block 0 Base Address = 0xFFFF0E00
Name FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1
Table 25. Flash/EE Block 1 Base Address = 0xFFFF0E80
Address 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E98 0x0E9C 0x0EA0 Name FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1
Table 26. PWM Base Address= 0xFFFF0F80 Table 23. GPIO Base Address = 0xFFFF0D00
Address 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D10 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D50 0x0D54 0x0D58 0x0D5C Name GP0CON GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP3DAT GP3SET GP3CLR GP3PAR Byte 4 4 4 4 4 4 1 1 4 4 1 1 4 4 1 1 4 1 1 4 Access Type R/W R/W R/W R/W R/W R/W W W R/W R/W W W R/W R/W W W R/W W W R/W Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8 Name
PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR
Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W
Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. PrA | Page 24 of 92
Preliminary Technical Data ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 3.0 V to 3.6 V supplies and is capable of providing a throughput of up to 1 MSPS when the clock source is 41.78 MHz. This block provides the user with a multichannel multiplexer, differential track-andhold, on-chip reference, and ADC. The ADC consists of a 12-bit successive approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of the following three modes: Fully differential mode, for small and balanced signals Single-ended mode, for any single-ended signals Pseudo differential mode, for any single-ended signals, taking advantage of the common mode rejection offered by the pseudo differential input
ADUC7122
Single or continuous conversion modes can be initiated in software. An external CONVST pin, an output generated from the on-chip PLA, a Timer0, or a Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions. If the signal has not been de-asserted by the time the ADC conversion is complete, a second conversion begins automatically. A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front-end ADC multiplexer, effectively an additional ADC channel input. This facilitates an internal temperature sensor channel, measuring die temperature to an accuracy of 3C. For the ADUC7122 a number of modifications have been made to the ADC input structure that appeared on the ADuC702x family. The PADC0 and PADC1 inputs connect to a PGA and allow for gain from 1 to 5 with 32 steps. The remaining channels can be configured as single or differential. A buffer is provided before the ADC for measuring internal channels.
The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage VCM, in the range 0 V to AVDD and with maximum amplitude of 2 VREF (see Figure 12).
AVDD VCM VCM 2VREF 2VREF
0
Figure 12. Examples of Balanced Signals for Fully Differential Mode
A high precision, low drift, and factory-calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described in the Band Gap Reference section.
06020-028
VCM
2VREF
Rev. PrA | Page 25 of 92
ADUC7122
ADC TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range is 0 to VREF. The output coding is straight binary in pseudo differential and single-ended modes with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV or 610 V when VREF = 2.5 V The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, ..., FS - 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 13.
1111 1111 1111 1111 1111 1110 1111 1111 1101
Preliminary Technical Data
SIGN BIT 0 1111 1111 1110 0 1111 1111 1100 0 1111 1111 1010 1LSB = 2 x VREF 4096
OUTPUT CODE
0 0000 0000 0001 0 0000 0000 0000 1 1111 1111 1110
1 0000 0000 0100 1 0000 0000 0010
06020-030
1 0000 0000 0000 -VREF + 1LSB 0LSB +VREF - 1LSB VOLTAGE INPUT (VIN+ - VIN-)
Figure 14. ADC Transfer Function in Differential Mode
PADC0/PADC1 in Optical Applications
An external precision resistor converts the current to voltage and the PGA then amplifies this voltage signal with gain up to 5 by 32 steps. The intention is to compensate the variation of the detector diode responsitivity and normalize optical power read by ADC. The external resistor is assumed to be 0.1% accuracy, 5 ppm. A 1 nF capacitor is shunted with the resistor to suppress wide band noise. The resistor value should be selected such that the FS voltage developed on the resistor is less than AVDD - 1.2 V, or typically 1.8 V.
+FS - 1LSB VOLTAGE INPUT
06020-029
OUTPUT CODE
1111 1111 1100 1LSB = FS 4096
0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 0V 1LSB
The PGA is designed to handle 10 mV minimum input. To minimize noise, the ADC input buffer should be bypassed. PADC1 is driven by a buffer to 0.15 V to keep the PGA from saturation when the input current drops to 0. The buffer can be disabled by setting ADCCON[14] so that the PADC1 can be connected to GND as well. This is the same for PADC0. The ADC needs to be placed in pseudo differential mode and assumes negative input is close to ground. All the controls are independently set through register bits to give maximum flexibility to the user. Typically, users need to set the following steps (using PADC1 as an example): 1. Select PADC1P as the PGA input, then select PGA output as mux input. Enable the PADC1N buffer and disable the ADC input buffer. Set the proper gain value for the PGA. Bypass the buffer. Set the ADC to pseudo differential mode and start conversion.
Figure 13. ADC Transfer Function in Pseudo Differential Mode or Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- inputs (that is, VIN+ - VIN-) of the currently enabled differential channel. The maximum amplitude of the differential signal is therefore -VREF to +VREF p-p (2 x VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals (VIN+ + VIN-)/2, and is, therefore, the voltage that the two inputs are centered on. This results in the span of each input being CM VREF/2. This voltage has to be set up externally, and its range varies with VREF (see the Driving the Analog Inputs section). The output coding is twos complement in fully differential mode with 1 LSB = 2 VREF/4096 or 2 x 2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The output result is 11 bits, but this is shifted by one to the right. This allows the result in ADCDAT to be declared as a signed integer when writing C code. The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, ..., FS - 3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 14.
2. 3.
All the controls are independently set through register bits for maximum flexibility to the user. Typically, users must set the following (using PADC0 as an example): Select PADC0P as PGA input, select PGA output as MUX input. Enable PADC0N buffer, disable ADC input buffer. Set proper gain value for the PGA; bypass the buffer ADC: set to pseudo differential mode, start conversion. Removing offset and 1/f noise requires performing two conversions on the input signal.
Rev. PrA | Page 26 of 92
Preliminary Technical Data
Set pga1_chop to 0 for the first conversion and pga1_chop = 1 for the second. Then calculate the average value.
ADUC7122
Calibration
By default, the factory-set values written to the ADC offset (ADCOF) and gain coefficient registers (ADCGN) yield optimum performance in terms of end-point errors and linearity for standalone operation of the part (see the Specifications section). If system calibration is required, it is possible to modify the default offset and gain coefficients to improve end-point errors, but note that any modification to the factory-set ADCOF and ADCGN values can degrade ADC linearity performance. For system offset error correction, the ADC channel input stage must be tied to AGND. A continuous software ADC conversion loop must be implemented by modifying the value in ADCOF until the ADC result (ADCDAT) reads Code 0 to Code 1. If the ADCDAT value is greater than 1, ADCOF should be decremented until ADCDAT reads Code 0 to Code 1. Offset error correction is performed digitally and has a resolution of 0.25 LSB and a range of 3.125% of VREF. For system gain error correction, the ADC channel input stage must be tied to VREF. A continuous software ADC conversion loop must be implemented to modify the value in ADCGN until ADCDAT reads Code 4094 to Code 4095. If the ADCDAT value is less than 4094, ADCGN should be incremented until ADCDAT reads Code 4094 to Code 4095. Similar to the offset calibration, the gain calibration resolution is 0.25 LSB with a range of 3% of VREF.
Thermistor and Other Input Channels
ADUC7122 provides 2 pairs of thermistor inputs and 7 extra differential input pins. These pins can also be configured as differential input pair or single ended input or pseudo differential inputs. The buffer and ADC are configured independently from input channel selection. Note that the input range of ADC input buffer is from 0.15V to AVDD-0.15V, if the input signal range exceeds this range, the input buffer must be bypassed. The ADUC7122 provide 2 pins for each thermistor input. The negative input is to remove error of ground difference. When selecting the thermistor input, the negative side buffer should always be bypassed to make sure the amplifier is not saturated. The ADC should be configured to work in positive pseudo differential mode. Besides these external inputs, ADC can also select internal inputs to monitor the IOVDD power supply. An on chip diode can also be selected to provide chip temperature monitoring. ADC can also select VREF and AGND as input for calibration purpose
PGA and Input Buffer
The PGA is a one stage positive gain amplifier that is be able to accept input from 0.1V to AVDD-1.2V and the output swing should be at least 2.5V. The gain of the PGA is from 1 to 5 with 32 linear steps. PGA cannot be bypassed for the PADC0 and PADC1 channels. The PGAs use PMOS input to minimize nonlinearity and noise. The input level for PGA is limited to AVDD-1.2V ~0.1V to make sure amplifiers are not saturated. The input buffer is railto-rail buffer. It can accept signal from 0.15V to AVDD-0.15V. Each of input buffers can be bypassed independently. The PGA can be chopped to remove offset and 1/f noise. The user need to manually chop the PGA for single conversion while it is automatically chopped when chop mode is enabled.
Current Consumption
The ADC in standby mode, that is, powered up but not converting, typically consumes 640 A. The internal reference adds 140 A. During conversion, the extra current is 0.3 A, multiplied by the sampling frequency (in kHz).
Timing
Figure 16 gives details of the ADC timing. Users control the ADC clock speed and the number of acquisition clock in the ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, giving a sampling rate of 774 kSPS. For conversion on the temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider is set to 32. When using multiple channels, including the temperature sensor, the timing settings revert back to the userdefined settings after reading the temperature sensor channel.
TYPICAL OPERATION
Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top four bits are the sign bits, and the 12-bit result is placed from Bit 16 to Bit 27, as shown in Figure 15. Again, it should be noted that in fully differential mode, the result is represented in twos complement format, and in pseudo differential and singleended mode, the result is represented in straight binary format.
31 27 16 15 0
06020-031
SIGN BITS
12-BIT ADC RESULT
Figure 15. ADC Result Format
Rev. PrA | Page 27 of 92
ADUC7122
ACQ BIT TRIAL WRITE
Preliminary Technical Data
TEMPERATURE SENSOR
The ADUC7122 provides a voltage output from an on-chip band gap reference proportional to absolute temperature. This voltage output can also be routed through the front-end ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel that measures die temperature. The internal temperature sensor is not designed for use as an absolute ambient temperature calculator. It is intended for use as an approximate indicator of the temperature of the ADUC7122 die.
06020-032
ADC CLOCK
CONVSTART
ADCBUSY
ADCDAT
DATA
ADCSTA = 0
ADCSTA = 1 ADC INTERRUPT
The typical temperature coefficient is -0.707 mV/C.
Figure 16. ADC Timing
ADC MMRs Interface
The ADC is controlled and configured via a number of MMRs (see Table 27) that are described in detail in the following pages.
ADC Output vs. Temperature
Table 27. ADC MMRs
Name ADCCON ADCCP ADCCN ADCSTA Description ADC control register. Allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC (either single-ended, pseudo differential, or fully differential mode), and to select the conversion type (see Table 28). ADC positive channel selection register. ADC negative channel selection register. ADC status register. Indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCREADY (Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt. It is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low. This information can be available on P0.5 (see the General-Purpose I/O section) if enabled in GP0CON register. ADC data result register. Holds the 12-bit ADC result, as shown Table 30. ADC reset register. Resets all the ADC registers to their default value. Gain of PADC0 and PADC1.
ADCDAT ADCRST PGA_GN
Rev. PrA | Page 28 of 92
Preliminary Technical Data
Table 28. ADCCON MMR Bit Designations (Address = 0xFFFF0500, Default Value = 0x00000A00)
Bit 31:16 15 Value
ADUC7122
0 1 14 0 1 13:11 000 001 010 011 100 101 10:8 000 001 010 011 100 101 7
6 5
4:3 00 01 10 11 2:0 000 001 010 011 100 101 110 Other
Description These bits are reserved. Positive ADC buffer bypass. Set to 0 by the user to enable the positive ADC buffer. Set to 1 by the user to bypass the positive ADC buffer. Negative ADC buffer bypass. Set to 0 by the user to enable the negative ADC buffer. Set to 1 by the user to bypass the negative ADC buffer. ADC clock speed (fADC = fCORE, conversion = 19 ADC clocks + acquisition time). fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz. fADC/2 (default value). fADC/4. fADC/8. fADC/16. fADC/32. ADC acquisition time (number of ADC clocks). 2 clocks. 4 clocks. 8 clocks (default value). 16 clocks. 32 clocks 64 clocks Enable conversion. Set by user to 1 to enable conversion mode. Cleared by user to 0 to disable conversion mode. Reserved. This bit should be set to 0 by the user. ADC power control. Set by user to 1 to place the ADC in normal mode. The ADC must be powered up for at least 5 s before it converts correctly. Cleared by user to 0 to place the ADC in power-down mode. Conversion mode. Single-ended mode. Differential mode. Pseudo differential mode. Reserved. Conversion type. Enable CONVST pin as a conversion input. Enable Timer1 as a conversion input. Enable Timer0 as a conversion input. Single software conversion. Automatically set to 000 after conversion. Continuous software conversion. PLA conversion. Reserved Reserved.
Rev. PrA | Page 29 of 92
ADUC7122
Table 29. ADCCP MMR Bit Designations (Address = 0xFFFF0504, Default Value = 0x00)
Bit 7:5 4:0 Value Description Reserved Positive channel selection bits PADC0P PADC1P ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM Temperature sensor Reserved Reserved Reserved Reserved Reserved IOVDD_MON Reserved Reserved VREF AGND Reserved
Preliminary Technical Data
Table 30. ADCCN MMR Bit Designations (Address = 0xFFFF0508, Default Value = 0x00)
Bit 7:5 4:0 Value Description Reserved Negative channel selection bits PADC0P PADC1P PADC0P PADC1P ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM PGND IOGND Reserved
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 Others
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others
Table 31. ADCSTA MMR Bit Designations (Address = 0xFFFF050C, Default Value = 0x00)
Bit 0 Value 1 Description Indicates that an ADC conversion is complete. It is set automatically once an ADC conversion completes. Automatically cleared by reading the ADCDAT MMR.
0
0
Table 32. ADCDAT MMR Bit Designations (Address = 0xFFFF0510, Default Value = 0x00000000)
Bit 27:16 Value Description Holds the ADC result (see Figure 15).
Table 33. ADCRST MMR Bit Designations (Address = 0xFFFF0514, Default Value = 0x00)
Bit 0 Value 1 Description Set to 1 by the user to reset all the ADC registers to their default values.
Table 34. PGA_GN MMR Bit Designations (Address = 0xFFFF0520, Default Value = 0x00)
Bit 11:6 5:0 Value Description Gain of PGA for PADC0 (PGA_PADC0_GN) = 1 + 4 x (PGA_ADC0_GN/32) Gain of PGA for PADC1 (PGA_PADC1_GN) = 1 + 4 x (PGA_ADC1_GN/32)
Note that PGA_PADC0_GN and PGA_PADC1_GN must be 32.
Rev. PrA | Page 30 of 92
Preliminary Technical Data
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described for the three different modes of operation: differential mode, pseudo differential mode, and single-ended mode.
ADUC7122
Pseudo Differential Mode
In pseudo differential mode, Channel- is linked to the VIN- input of the ADUC7122, and SW2 switches between A (Channel-) and B (VREF). The VIN- input must be connected to ground or a low voltage. The input signal on VIN+ can then vary from VIN- to VREF + VIN-. Note that VIN- must be selected so that VREF + VIN- does not exceed AVDD.
CAPACITIVE DAC AIN0 MUX AIN11 A B VIN- CAPACITIVE DAC
06020-035 06020-036
Differential Mode
The ADUC7122 contains a successive approximation ADC based on two capacitive DACs. Figure 17 and Figure 18 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC comprises control logic, a SAR, and two capacitive DACs. In Figure 17 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A. The comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.
CAPACITIVE DAC AIN0 MUX AIN11 CHANNEL- A SW2 B CAPACITIVE DAC
06020-033
CHANNEL+
B A SW1 SW2
CS
COMPARATOR
CS
SW3
CONTROL LOGIC
VREF CHANNEL-
Figure 19. ADC in Pseudo Differential Mode
B A SW1 CS SW3 CS COMPARATOR
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to ground. The VIN- input can be floating. The input signal range on VIN+ is 0 V to VREF.
CAPACITIVE DAC AIN0 MUX AIN11 CHANNEL- CHANNEL+ B A SW1 CS SW3 CS COMPARATOR
CHANNEL+
CONTROL LOGIC
VREF
Figure 17. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 18), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the VIN+ and VIN- inputs must be matched; otherwise, the two inputs have different settling times, resulting in errors.
CAPACITIVE DAC AIN0 MUX AIN11 CHANNEL- A SW2 B CAPACITIVE DAC
06020-034
CONTROL LOGIC
CAPACITIVE DAC
Figure 20. ADC in Single-Ended Mode
Analog Input Structure
Figure 21 shows the equivalent circuit of the analog input structure of the ADC. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. Voltage in excess of 300 mV can cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The C1 capacitors in Figure 21 are typically 4 pF and can be primarily attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 . The C2 capacitors are the ADC sampling capacitors and have a capacitance of 16 pF typical.
CHANNEL+
B A SW1
CS
COMPARATOR
CS
SW3
CONTROL LOGIC
VREF
Figure 18. ADC Conversion Phase
Rev. PrA | Page 31 of 92
ADUC7122
AVDD D R1 C2
Preliminary Technical Data
DRIVING THE ANALOG INPUTS
Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on the common-mode input signal (VCM) that are dependent on reference value and supply voltage used to ensure that the signal remains within the supply rails. Table 35 gives some calculated VCM minimum and VCM maximum values. Table 35. VCM Ranges
06020-037
C1
D
AVDD D
R1 C2
C1
D
Figure 21. Equivalent Analog Input Circuit Conversion Phase: Switches Open, Track Phase: Switches Closed
AVDD 3.3 V
For ac applications, removing high frequency components from the analog input signal is recommended through the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and can necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Figure 22 and Figure 23 give an example of an ADC front end.
ADUC7122
3.0 V
VREF 2.5 V 2.048 V 1.25 V 2.5 V 2.048 V 1.25 V
VCM Min 1.25 V 1.024 V 0.75 V 1.25 V 1.024 V 0.75 V
VCM Max 2.05 V 2.276 V 2.55 V 1.75 V 1.976 V 2.25 V
Signal Peak-to-Peak 2.5 V 2.048 V 1.25 V 2.5 V 2.048 V 1.25 V
10W 0.01mF
ADC0
Figure 22. Buffering Single-Ended/Pseudo Differential Input Figure 24. ADC Output vs. Temperature
ADUC7122 ADC0 Vref ADC1
Figure 23. Buffering Differential Inputs
When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and the performance degrades.
Rev. PrA | Page 32 of 92
Preliminary Technical Data
BAND GAP REFERENCE
The ADUC7122 provide an on-chip band gap reference of 2.5 V that can be used for the ADC and for the DAC. This 2.5 V reference is generated from a 1.2V reference. This internal reference also appears on the VREF_2.5pin. When using the internal reference, two 0.47 F capacitors must be connected from the external VBREFB 2.5 V and VBREFB 1.2 V pins to AGND to ensure stability and fast response during ADC conversions. This reference can also be connected to an external pin (VREF) and used as a reference for other circuits in the system. The band gap reference also connects through buffers to the BUF_VREF1 and the BUF_VREF2 pins. A minimum of 0.1 F capacitor should be connected to these pins to damp noise. The band gap reference interface consists of an 8-bit REFCON MMR, described in Table 36.
ADUC7122
generated until CMP returns high. The user should ensure that code execution remains within the ISR until CMP returns high. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply or brown-out conditions. It also ensures that normal code execution does not resume until a safe supply level has been established. When the ADC channel selection bits are configured to IOVDD_MON, this permits the ADC to convert the voltage available at the input of the power supply monitor comparator. When measuring an internal channel, the internal buffer should be enabled. The internal buffer should be enabled to isolate the external interference when sampling any of the internal channels. Before measuring this voltage, the following sequence is required. 1. 2. 3. 4. Measure VREF using the ADC. Set ADCCP = IOVDD_MON channel. Set a typical delay of 60 s. Perform ADC conversion on the IOVDD_MON channel (Use anADCCON value of 0x2AA3 for optimum results).
POWER SUPPLY MONITOR
The power supply monitor on the ADUC7122 indicates when the IOVBDDB supply pin drops below one of two supply trip points. The monitor function is controlled via the PSMCON register. If enabled in the IRQEN or FIQEN register, the monitor interrupts the core using the PSMI bit in the PSMCON MMR. This bit is cleared immediately when CMP goes high. Note that if the interrupt generated is exited before CMP goes high (IOVDD is above the trip point), no further interrupts are
Bit 7:1 2 1
The delay between the ADC mux select switching and the initiation of the conversion is required to allow the voltage on the ADC sampling capacitor to settle to the divided down supply voltage.
Table 36. REFCON MMR Bit Designations (Address = 0xFFFF0480, Default Value = 0x01)
Description Reserved. BUF_VREF is driven from the internal 2.5 V reference when set to 1. Internal 2.5 V reference output enable. Set by user to connect the internal 2.5 V reference to the VREF_2.5 pin. Cleared by user to disconnect the reference from the VREF_2.5 pin. This pin should also be cleared to connect an external reference source to the VREF_2.5 pin. Internal 1.2 V reference output enable. Set by user to connect the internal 1.2 V reference to the VREF_1.2 pin. Cleared by user to disconnect the reference from the VREF_1.2 pin.
0
Table 37. PSMCON MMR Bit Designations (Address = 0xFFFF0440, Default Value = 0x08 or 0x00 (Dependent on Device Supply Level)
Bit 3 Name CMP Description Comparator bit. This is a read-only bit that directly reflects the state of the comparator. Read 1 indicates the IOVBDDB supply is above its selected trip point or the PSM is in power-down mode. Read 0 indicates the IOVBDDB supply is below its selected trip point. This bit should be set before leaving the interrupt service routine. Trip point selection bit. 0 = 2.79 V 1 = 3.07 V Power supply monitor enable bit. Set to 1 by the user to enable the power supply monitor circuit. Cleared to 0 by the user to disable the power supply monitor circuit. Power supply monitor interrupt bit. This bit is set high by the MicroConverter(R) if CMP is low, indicating low I/O supply. The PSMI Bit can be used to interrupt the processor. Once CMP returns high, the PSMI bit can be cleared by writing a 1 to this location. A write of 0 has no effect. There is no timeout delay. PSMI can be cleared immediately once CMP goes high.
Rev. PrA | Page 33 of 92
2
TP
1
PSMEN
0
PSMI
ADUC7122 NONVOLATILE FLASH/EE MEMORY
FLASH/EE MEMORY OVERVIEW
The ADUC7122 incorporates Flash/EE memory technology onchip to provide the user with non-volatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, Flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes no volatility, in-circuit programmability, high density, and low cost. Incorporated in the ADUC7122, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes.
Preliminary Technical Data
As indicated in the Specifications section, the Flash/EE memory endurance qualification is carried out in accordance with JEDEC Retention Lifetime Specification A117 over the industrial temperature range of -10 to +95C. The results allow the specification of a minimum endurance figure over a varying supply across the industrial temperature range for 10,000 cycles. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts are qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 85C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. Note, too, that retention lifetime, based on activation energy of 0.6 eV, derates with TJ, as shown in Figure 25.
600
FLASH/EE MEMORY
The ADUC7122 contains two 64 kB arrays of Flash/EE memory. In the upper block of Flash/EE memory, the bottom 62 Kb are available to the user and the top 2 kB of this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download. The 2 Kb of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals (band gap references and so on). This 2 kB embedded firmware is hidden from user code. It is not possible for the user to read, write, or erase this page. In the second block, all 64 kB of Flash/EE memory are available to the user. The 126 kB of Flash/EE memory can be programmed in-circuit, using the serial download mode or the JTAG mode provided.
RETENTION (Years)
450
300
150
04955-085
0
30
40
55 70 85 100 125 JUNCTION TEMPERATURE (C)
135
150
Flash/EE Memory Reliability
The Flash/EE memory arrays on the ADUC7122 is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as 1. 2. 3. 4. Initial page erase sequence Read/verify sequence a single Flash/EE Byte program sequence memory Second read/verify sequence endurance cycle
Figure 25. Flash/EE Memory Data Retention
Serial Downloading (In-Circuit Programming)
The ADUC7122 facilitates code download via the I2C serial port. The ADUC7122 enters serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1 k resistor. This is combined with the state of address 0x00014 in the flash. If this address is 0xFFFFFFFF and the BM pin is pulled low the part will enter download mode, if this address contains any other value user code is executed. Once in serial download mode, the user can download code to the full 126 kB of Flash/EE memory while the device is in-circuit in its target application hardware. A PC serial download executable and hardware dongle are provided as part of the development system for serial downloads via the I2C port.
In reliability qualification, three separate page blocks from each Flash/EE memory block is tested. An entire Flash/EE page at the top, middle, and bottom of each Flash/EE memory block is cycled 10,000 times from 0x0000 to 0xFFFF.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug.
Rev. PrA | Page 34 of 92
Preliminary Technical Data
FLASH/EE MEMORY SECURITY
The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR protects the 126 kB from being read through JTAG and also in parallel programming mode. The other 31 bits of this register protect writing to the Flash/EE memory; each bit protects four pages, that is, 2 kB. Write protection is activated for all access types. FEE1PRO and FEE1HID similarly protect the second 64 kB block. All 32 bits of this are used to protect four pages at a time.
ADUC7122
The sequence to write the key is shown in the following example; this protects writing Page 4 to Page 7 of the Flash/EE memory:
FEE0PRO=0xFFFFFFFD; FEE0MOD=0x48; FEE0ADR=0x1234; FEE0DAT=0x5678; FEE0CON= 0x0C; //Protect pages 4 to 7 //Write key enable //16 bit key value //16 bit key value // Write key command
The same sequence should be followed to protect the part permanently with FEExADR = 0xDEAD and FEExDAT = 0xDEADDEAD.
Three Levels of Protection
Protection can be set and removed by writing directly into FEExHID MMR. This protection does not remain after reset. Protection can be set by writing into FEExPRO MMR. It takes effect only after a save protection command (0x0C) and a reset. The FEExPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEExPRO. A mass erase sets the key back to 0xFFFF but also erases all the user code. The Flash/EE memory can be permanently protected by using the FEEPRO MMR and a particular value of the 0xDEADDEAD key. Entering the key again to modify the FEExPRO register is not allowed.
FLASH/EE CONTROL INTERFACE
Table 38. FEE0DAT Register
Name FEE0DAT Address 0xFFFF0E0C Default Value 0xXXXX Access R/W
FEE0DAT is a 16-bit data register. Table 39. FEE0ADR Register
Name FEE0ADR Address 0xFFFF0E10 Default Value 0x0000 Access R/W
FEE0ADR is a 16-bit address register. Table 40. FEE0SGN Register
Name FEE0SGN Address 0xFFFF0E18 Default Value 0xFFFFFF Access R
Sequence to Write the Key
1. 2. 3. 4. 5. Write the bit in FEExPRO corresponding to the page to be protected. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 must equal 0). Write a 32-bit key in FEExADR, FEExDAT. Run the write key command 0x0C in FEExCON; wait for the read to be successful by monitoring FEExSTA. Reset the part.
FEE0SGN is a 24-bit code signature. Table 41. FEE0PRO Register
Name FEE0PRO Address 0xFFFF0E1C Default Value 0x00000000 Access R/W
To remove or modify the protection, the same sequence is used with a modified value of FEExPRO. If the key chosen is the value 0xDEADDEAD, then the memory protection cannot be removed. Only a mass erase unprotects the part; however, it also erases all user code.
FEE0PRO provides protection following subsequent reset MMR. It requires a software key (see Table 57). As stated previously, each bit from 30 to 0 of the FEEXPRO register protects a 2 kB block of memory; that is, setting Bit 0 low protects Page 0 to Page 3 and setting Bit 2 low protects Page 8 to Page 11. Table 42. FEE0HID Register
Name FEE0HID Address 0xFFFF0E20 Default Value 0xFFFFFFFF Access R/W
FEE0HID provides immediate protection MMR. It does not require any software keys (see Table 57).
Command Sequence for Executing a Mass Erase
FEE0DAT = 0x3CFF; FEE0ADR = 0xFFC3; FEE0MOD = FEE0MOD|0x8; //Erase key enable FEE0CON = 0x06; //Mass erase command
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ADUC7122
Table 43. FEE1DAT Register
Name FEE1DAT Address 0xFFFF0E8C Default Value 0xXXXX Access R/W
Preliminary Technical Data
FEE1HID provides immediate protection MMR. It does not require any software keys (see Table 58). Table 48. FEE0STA Register
Name FEE0STA Access R/W Address 0xFFFF0E00 Default Value 0x0000 Access RW
FEE1DAT is a 16-bit data register. Table 44. FEE1ADR Register
Name FEE1ADR Address 0xFFFF0E90 Default Value 0x0000
Table 49. FEE1STA Register
Name FEE1STA Address 0xFFFF0E80 Default Value 0x0000 Access RW
FEE1ADR is a 16-bit address register. Table 45. FEE1SGN Register
Name FEE1SGN Address 0xFFFF0E98 Default Value 0xFFFFFF Access R
Table 50. FEE0MOD Register
Name FEE0MOD Address 0xFFFF0E04 Default Value 0x80 Access RW
FEE1SGN is a 24-bit code signature. Table 46. FEE1PRO Register
Name FEE1PRO Address 0xFFFF0E9C Default Value 0x00000000 Access R/W
Table 51. FEE1MOD Register
Name FEE1MOD Address 0xFFFF0E84 Default Value 0x80 Access RW
Table 52. FEE0CON Register
Name FEE0CON Address 0xFFFF0E08 Default Value 0x0000 Access RW
FEE1PRO provides protection following subsequent reset MMR. It requires a software key (see Table 58). Table 47. FEE1HID Register
Name FEE1HID Address 0xFFFF0EA0 Default Value 0xFFFFFFFF Access RW
Table 53. FEE1CON Register
Name FEE1CON Address 0xFFFF0E88 Default Value 0x0000 Access RW
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Preliminary Technical Data
Table 54. FEExSTA MMR Bit Designations
Bit 15:6 5 4 3
ADUC7122
2
1
0
Description Reserved. Reserved. Reserved. Flash/EE interrupt status bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set. Cleared when reading FEExSTA register. Flash/EE controller busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Command fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading FEExSTA register. Command complete. Set by MicroConverter when a command is complete. Cleared automatically when reading FEExSTA register.
Table 55. FEExMOD MMR Bit Designations
Bit 7:5 4 Description Reserved. Flash/EE interrupt enable. Set by user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by user to disable the Flash/EE interrupt Erase/write command protection. Set by user to enable the erase and write commands. Cleared to protect the Flash/EE memory against erase/write command. Reserved. Should always be set to 0 by the user. Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect.
3
2 1:0
Table 56. Command Codes in FEExCON
Code 0x001 0x011 0x021 0x031 0x041 0x051 0x061 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
1
Command Null Single read Single write Erase/write Single verify Single erase Mass erase Reserved Reserved Reserved Reserved Signature Protect Reserved Reserved Ping
Description Idle state. Load FEExDAT with the 16-bit data indexed by FEExADR. Write FEExDAT at the address pointed by FEExADR. This operation takes 50 s. Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms. Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA Bit 1. Erase the page indexed by FEExADR. Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental execution, a command sequence is required to execute this instruction. Reserved. Reserved. Reserved. Reserved. Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles. This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key. Reserved. Reserved. No operation, interrupt generated.
The FEExCON register always reads 0x07 immediately after execution of any of these commands.
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ADUC7122
Table 57. FEE0PRO and FEE0HID MMR Bit Designations
Bit 31
Preliminary Technical Data
30:0
Description Read Protection. Cleared by user to protect Block 0. Set by user to allow reading Block 0. Write Protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 0 to Page 3. Cleared by user to protect the pages in writing. Set by user to allow writing the pages.
Table 58. FEE1PRO and FEE1HID MMR Bit Designations
Bit 31 Description Read Protection. Cleared by user to protect Block 1. Set by user to allow reading Block 1. Write Protection for Page 127 to Page 120. Cleared by user to protect the pages in writing. Set by user to allow writing the pages. Write Protection for Page 119 to Page 116 and for Page 0 to Page 3. Cleared by user to protect the pages in writing. Set by user to allow writing the pages.
30
31:0
EXECUTION TIME FROM SRAM AND FLASH/EE
This section describes SRAM and Flash/EE access times during execution of applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because the access time of the SRAM is 2 ns and a clock cycle is 22 ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM (or three cycles if the data is in Flash/EE), one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction, such as a branch instruction, takes one cycle to fetch, but it also takes two cycles to fill the pipeline with the new instructions.
Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipeline. A data processing instruction involving only core registers doesn't require any extra clock cycles, but if it involves data in Flash/EE, an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instructions are more complex and are summarized in Table 59. Table 59. Execution Cycles in ARM/Thumb Mode
Instructions LD LDH LDM/PUSH STR STRH STRM/POP Fetch Cycles 2/1 2/1 2/1 2/1 2/1 2/1 Dead Time 1 1 N 1 1 N Data Access 2 1 2xN 2 x 20 s 20 s 2 x N x 20 s Dead Time 1 1 N 1 1 N
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit words is 23 ns, execution from Flash/EE cannot be completed in one cycle (contrary to a SRAM fetch, which can be completed in a single cycle when CD bits = 0). Dependent on the instruction, some dead times may be required before accessing data for any value of CD bits. In ARM mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when CD = 0. In Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction.
With 1 < N 16, N is the number of bytes of data to load or store in the multiple load/store instruction. The SWAP instruction combines an LD and STR instruction with only one fetch, giving a total of eight cycles plus 40 s.
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Preliminary Technical Data
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020, as shown in Figure 26.
FFFFFFFFh
ADUC7122
Remap Operation
When a reset occurs on the ADUC7122, execution starts automatically in factory-programmed internal configuration code. This kernel is hidden and cannot be accessed by user code. If the ADUC7122 is in normal mode (the BM pin is high), it executes the power-on configuration routine of the kernel and then jumps to the reset vector Address 0x00000000 to execute the user's reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in Flash/EE. The memory remap from Flash/EE is configured by setting Bit 0 of the REMAP register. Precautions must be taken to execute this command from Flash/EE, above Address 0x00080020, and not from the bottom of the array because this is replaced by the SRAM. This operation is reversible: the Flash/EE can be remapped at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. Precaution must again be taken to execute the remap function from outside the mirrored area. Any kind of reset remaps the Flash/EE memory at the bottom of the array.
kernel interrupt service routines
0009F800h
Flash/EE
00080000h
00041FFFh interrupt service routines
SRAM
00040000h
Mirror Space
ARM exception vector addresses
0x00000020 0x00000000 00000000h
Figure 26. Remap for Exception Execution
By default and after any reset, the Flash/EE is mirrored at the bottom of the memory array. The remap function allows the programmer to mirror the SRAM at the bottom of the memory array, facilitating execution of exception routines from SRAM instead of from Flash/EE. This means exceptions are executed twice as fast, with the exception being executed in ARM mode (32 bits), and the SRAM being 32 bits wide instead of 16-bit wide Flash/EE memory.
Reset Operation
There are four types of reset: external reset, power-on reset, watchdog expiration, and software force reset. The RSTSTA register indicates the source of the last reset and RSTCLR clears the RSTSTA register. These registers can be used during a reset exception service routine to identify the source of the reset. If RSTSTA is null, the reset was external. Note that when clearing RSTSTA, all bits that are currently 1 must be cleared. Otherwise, a reset event occurs.
Table 60. REMAP MMR Bit Designations (Address = 0xFFFF0220, Default Value = 0x00)
Bit 0 Name Remap Description Remap bit. Set by user to remap the SRAM to Address 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to address 0x00000000.
Table 61. RSTSTA MMR Bit Designations (Address = 0xFFFF0230, Default Value = 0x0X)
Bit 7:3 2 Description Reserved. Software reset. Set by user to force a software reset. Cleared by setting the corresponding bit in RSTCLR. Watchdog timeout. Set automatically when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. Power-on reset. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR.
1
0
Rev. PrA | Page 39 of 92
ADUC7122 OTHER ANALOG PERIPHERALS
DAC
The ADUC7122 incorporates 12 buffered 12-bit voltage output string DACs on-chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 k/100 pF. Each DAC has three selectable ranges: 0 V to VREF (internal band gap 2.5 V reference), 0 V to DACREF, and 0 V to Ext Ref.
Preliminary Technical Data
The signal range is 0 V to AVDD. To note that the DAC can also operate in interpolation mode.
MMRs Interface
Each DAC is independently configurable through a control register and a data register. These two registers are identical for the twelve DACs. Only DACxCON and DACxDAT (see Table 62 to Table 65) are described in detail in this section.
Figure 27. DAC Configuration
Figure 28. DAC User Functionality
Table 62 DACxCON Registers
Name DAC0CON DAC1CON DAC2CON DAC3CON DAC4CON DAC5CON DAC6CON DAC7CON DAC8CON DAC9CON DAC10CON DAC11CON Address 0xFFFF0580 0xFFFF0588 0xFFFF0590 0xFFFF0598 0xFFFF05A0 0xFFFF05A8 0xFFFF05B0 0xFFFF05B8 0xFFFF05C0 0xFFFF05C8 0xFFFF05D0 0xFFFF05D8 Default Value 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100 0x100
Rev. PrA | Page 40 of 92
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Preliminary Technical Data
Table 63. DACxCON MMR Bit Designations
Bit 15:9 8 7 6 5 4 3 2 1:0 Value 0 1 0 0 0 0 0 0 00 01 10 11 Name DACPD DACBUF_LP BYP DACCLK DACCLR MODE RATE DACRNx
ADUC7122
Description Reserved. DAC power-down. Set by user to set DACOUTx to tri-state mode. DAC buffer low power mode. Set by user to place DAC_BUFF in a low power mode. DAC bypass bit. Set this bit to bypass the DAC buffer. Cleared to buffer the DAC output. DAC update rate. Set by user to update the DAC using Timer1. Cleared by user to update the DAC using HCLK (core clock). DAC clear bit. Set by user to enable normal DAC operation. Cleared by user to reset data register of the DAC to 0. Mode bit. Set by user to operate on DAC normal mode and turn off the interpolator clock source. Cleared by user to enable the interpolation mode. Rate bit. Set by user to enable the interpolation clock to HCLK/16. Cleared by user to HCLK/32. DAC range bits. Int_ref/AGND. Ext_ref/AGND. Ext_ref/AGND. AVDD/AGND.
Table 64. DACxDAT Registers
Name DAC0DAT DAC1DAT DAC2DAT DAC3DAT DAC4DAT DAC5DAT DAC6DAT DAC7DAT DAC8DAT DAC9DAT DAC10DAT DAC11DAT Address 0xFFFF0584 0xFFFF058C 0xFFFF0594 0xFFFF059C 0xFFFF05A4 0xFFFF05AC 0xFFFF05B4 0xFFFF05BC 0xFFFF05C4 0xFFFF05CC 0xFFFF05D4 0xFFFF05DC Default Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 65. DACxDAT MMR Bit Designations
Bit 31:28 27:16 15:12 11:0 Description Reserved. 12-bit data for DACx. Extra bits for Interpolation Mode. Reserved.
Rev. PrA | Page 41 of 92
ADUC7122
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier. The functional equivalent is shown in Figure 29.
AVDD VREF DACREF R R R
AVDD AVDD - 100mV
Preliminary Technical Data
0x00000000
0x0FFF0000
Figure 30. Endpoint Nonlinearities Due to Amplifier Saturation
R R
04955-023
Figure 29. DAC Structure
As illustrated in Figure 29, the reference source for each DAC is user-selectable in software. It can be either AVDD or VREF. In 0-toAVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In 0-to-VREF mode, the DAC output transfer function spans from 0 V to the internal 2.5 V reference, VREF. The DAC output buffer amplifier features a true, rail-to-rail output stage implementation. This means that when unloaded, each output is capable of swinging to within less than 5 mV of both AVDD and ground. Moreover, the DAC's linearity specification (when driving a 5 k resistive load to ground) is guaranteed through the full transfer function except codes 0 to 100, and, in 0-to-AVDD mode only, codes 3995 to 4095. Linearity degradation near ground and VDD is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 30. The dotted line in Figure 30 indicates the ideal transfer function, and the solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 30 represents a transfer function in 0-to-AVDD mode only. In 0-to-VREF or 0-to-DACREF modes (with VREF < AVDD or DACREF < AVDD), the lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line right to the end (VREF in this case, not AVDD), showing no signs of endpoint linearity errors.
The endpoint nonlinearities conceptually illustrated in Figure 30 get worse as a function of output loading. The ADUC7122 data sheet specifications assume a 5 k resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 30 become larger. With larger current demands, this can significantly limit output voltage swing.
LDO (LOW DROPOUT REGULATOR)
The ADUC7122 contains an integrated LDO which generates the core supply voltage (LVDD) of approximately 2.6V from the IOVDD supply. As the LDO is driven from the IOVDD, the IOVDD supply voltage needs to be greater than 2.7V. An external compensation capacitor (CT) of 0.47 F with low equivalent series resistance (ESR) must be placed very close to LVDD pin. This capacitor also acts as a storage of charge and supplies an instantaneous charge required by the core particularly at positive edge of core clock (HCLK). The LVDD voltage generated by the LDO is solely for providing a supply for the ADUC7122. Therefore, users should not use LVDD pin as the power supply pin for any other chip. Also, it is recommended that the IOVDD pin have excellent power supply decoupling, in order to help improve line regulation performance of the LDO. The LVDD pin has no reverse battery, current limit or thermal shutdown protection; therefore, it is essential that users of the ADUC7122 do not short this pin to ground at anytime during normal operation or during board manufacture.
Rev. PrA | Page 42 of 92
04955-024
DAC0
100mV
Preliminary Technical Data OSCILLATOR AND PLL--POWER CONTROL
The ADUC7122 integrates a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving. The default core clock is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core clock frequency can be output on the XCLK pin as described in Figure 31. Note that when the XCLK pin is used to output the core clock, the output signal is not buffered and is not suitable for use as a clock source to an external device without an external buffer. A power-down mode is available on the ADUC7122. The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs, PLLCON (see Table 72) and POWCON (see Table 73). PLLCON controls the operating mode of the clock system, and POWCON controls the core clock frequency and the power-down mode.
POWKEY1 = 0x01; POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4;
ADUC7122
Example Source Code
T2LD = 5; TCON = 0x480; while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x01; PLLKEY2 = 0x55;
In noisy environments, noise can couple to the external crystal pins, and PLL may lose lock momentarily. A PLL interrupt is provided in the interrupt controller. The core clock is immediately halted, and this interrupt is serviced only when the lock is restored. In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer.
EXTERNAL CLOCK SELECTION
To switch to an external clock on P1.4, configure P1.4 in Mode 2. The external clock can be up to 41.78 MHz, providing the tolerance is 1%.
Example Source Code
T2LD = 5; TCON = 0x480;
Figure 31. Clocking System
while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x03; //Select external clock PLLKEY2 = 0x55; POWKEY1 = 0x01; POWCON = 0x27; // Set Core into Nap mode POWKEY2 = 0xF4;
EXTERNAL CRYSTAL SELECTION
To switch to an external crystal, users must use the following procedure: 1. 2. 3. 4. Enable the Timer2 interrupt and configure it for a timeout period of >120 s. Follow the write sequence to the PLLCON register, setting the MDCLK bits to 01 and clearing the OSEL bit. Force the part into nap mode by following the correct write sequence to the POWCON register. When the part is interrupted from nap mode by the Timer2 interrupt source, the clock source has switched to the external clock.
Rev. PrA | Page 43 of 92
ADUC7122
POWER CONTROL SYSTEM
A choice of operating modes is available on the ADUC7122. Table 66 describes which blocks of the ADUC7122 are powered on in the different modes and indicates the power-up time. Table 67 gives some typical values of the total current consumption Table 66. Operating Modes
Mode Active Pause Nap Sleep Stop PC[2-0] 000 001 010 011 100 Core On Peripherals On On PLL On On On XTAL/Timer 2/Timer 3 On On On On XIRQ On On On On On CD = 4 8.1 4.9 3.8 0.25 0.25
Preliminary Technical Data
(analog + digital supply currents) in the different modes, depending on the clock divider bits when the ADC is turned off. The ADC is turned off. Note that these values also include current consumption of the regulator and other parts on the test board on which these values were measured.
Start-Up/Power-On Time 130 ms at CD = 0 24 ns at CD = 0; 3.06 s at CD = 7 24 ns at CD = 0; 3.06 s at CD = 7 1.58 ms 1.7 ms CD = 5 7.2 4.3 3.8 0.25 0.25 CD = 6 6.7 4 3.8 0.25 0.25 CD = 7 6.45 3.85 3.8 0.25 0.25
Table 67. Typical Current Consumption at 25C
Mode Active Pause Nap Sleep Stop CD = 0 30 22.7 3.8 0.25 0.25 CD = 1 21.2 13.3 3.8 0.25 0.25 CD = 2 13.8 8.5 3.8 0.25 0.25 CD = 3 11 6.1 3.8 0.25 0.25
Rev. PrA | Page 44 of 92
ADUC7122
MMRS AND KEYS
To prevent accidental programming, a certain sequence must be followed when writing in the PLLCON and POWCON registers (see Table 72). Table 68. PLLKEYx Register
Name PLLKEY1 PLLKEY2 Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access W W 4:2 1:0 Bit 7:6 5 Value
Preliminary Technical Data
Table 73. PLLCON MMR Bit Designations
Name OSEL Description Reserved. 32 kHz PLL Input Selection. Set by user to use the internal 32 kHz oscillator. Set by default. Cleared by user to use the external 32 kHz crystal. Reserved. Clocking modes. Reserved. PLL. default configuration. Reserved. External clock on P1.4 pin.
MDCLK 00 01 10 11
Table 69. PLLCON Register
Name PLLCON Address 0xFFFF0414 Default Value 0x21 Access R/W
Table 70. POWKEYx Register
Name POWKEY1 POWKEY2 Address 0xFFFF0404 0xFFFF040C Default Value 0x0000 0x0000 Access W W
Table 74. POWCON MMR Bit Designations
Bit 7 6:4 Value Name PC 000 001 010 011 100 Others 3 2:0 000 001 010 011 100 101 110 111 RSVD CD Description Reserved. Operating modes. Active mode. Pause mode. Nap. Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the ADUC7122. Stop mode. Reserved. Reserved. CPU clock divider bits. 41.779200 MHz. 20.889600 MHz. 10.444800 MHz. 5.222400 MHz. 2.611200 MHz. 1.305600 MHz. 654.800 kHz. 326.400 kHz.
Table 71. POWCON Register
Name POWCON Address 0xFFFF0408 Default Value 0x0003 Access R/W
Table 72. PLLCON and POWCON Write Sequence
PLLCON PLLKEY1 = 0xAA PLLCON = 0x01 PLLKEY2 = 0x55 POWCON POWKEY1 = 0x01 POWCON = user value POWKEY2 = 0xF4
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ADUC7122 DIGITAL PERIPHERALS
PWM GENERAL OVERVIEW
The ADUC7122 integrates a six channel PWM interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power up, the PWM outputs default to H-bridge mode. This ensures that the H-bridge controlled motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins. Users have control over the period of each pair of outputs and over the duty cycle of each individual output. Table 75. PWM MMRs
Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Function PWM Control Compare Register 1 for PWM Output 1 and Output 2 Compare Register 2 for PWM Output 1 and Output 2 Compare Register 3 for PWM Output 1 and Output 2 Frequency Control for PWM Output 1 and Output 2 Compare Register 1 for PWM Output 3 and Output 4 Compare Register 2 for PWM Output 3 and Output 4 Compare Register 3 for PWM Output 3 and Output 4 Frequency Control for PWM Output 3 and Output 4 Compare Register 1 for PWM Output 5 and Output 6 Compare Register 2 for PWM Output 5 and Output 6 Compare Register 3 for PWM Output 5 and Output 6 Frequency Control for PWM Output 5 and Output 6 PWM Convert Start Control PWM Interrupt Clear
HIGH SIDE (PWM1)
Preliminary Technical Data
LOW SIDE (PWM2)
PWM1COM3 PWM1COM2 PWM1COM1 PWM1LEN
06020-044
Figure 32. PWM Timing
The PWM clock is selectable via PWMCON1 with one of the following values: UCLK/2, 4, 8, 16, 32, 64, 128, or 256. The length of a PWM period is defined by PWMxLEN. The PWM waveforms are set by the count value of the 16-bit timer and the compare registers contents as shown with the PWM1 and PWM2 waveforms in Figure 32. The low-side waveform, PWM2, goes high when the timer count reaches PWM1LEN, and it goes low when the timer count reaches the value held in PWM1COM3 or when the high-side waveform PWM1 goes low. The high-side waveform, PWM1, goes high when the timer count reaches the value held in PWM1COM1, and it goes low when the timer count reaches the value held in PWM1COM2. In H-bridge mode, HMODE = 1 and Table 76 determine the PWM outputs.
In all modes, the PWMxCOMx MMRs controls the point at which the PWM outputs change state. An example of the first pair of PWM outputs (PWM1 and PWM2) is shown in Figure 32.
Table 76. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012)
Bit 15 14 Name Reserved SYNC Description This bit is reserved Enables PWM synchronization. Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the SYNC pin. Cleared by user to ignore transitions on the SYNC pin. Set to 1 by the user to invert PWM6. Cleared by user to use PWM6 in normal mode. Set to 1 by the user to invert PWM4. Cleared by user to use PWM4 in normal mode. Set to 1 by the user to invert PWM2. Cleared by user to use PWM2 in normal mode. Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an interrupt is generated. Cleared by user to disable the PWMTRIP interrupt. If HOFF = 0 and HMODE = 1. Set to 1 by the user to enable PWM outputs. Cleared by user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 77. If not in H-Bridge mode, this bit has no effect. PWM clock prescaler bits.
Rev. PrA | Page 46 of 92
13 12 11 10
PWM6INV PWM4NV PWM2INV PWMTRIP
9
ENA
8
PWMCP2
Preliminary Technical Data
Bit 7 6 Name PWMCP1 PWMCP0 Description Sets UCLK divider.
ADUC7122
5 4
POINV HOFF
3
LCOMP
2
DIR
1
HMODE
0
PWMEN
2. 4. 8. 16. 32. 64. 128. 256. Set to 1 by the user to invert all PWM outputs. Cleared by user to use PWM outputs as normal. High-side off. Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low. Cleared by user to use the PWM outputs as normal. Load compare registers. Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by user to use the values previously stored in the internal compare registers. Direction control. Set to 1 by the user to enable PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low. Cleared by user to enable PWM3 and PWM4 as the output signals while PWM1 and PWM2 are held low. Enables H-bridge mode. Set to 1 by the user to enable H-Bridge mode and Bit 1 to Bit 5 of PWMCON1. Cleared by user to operate the PWMs in standard mode. Set to 1 by the user to enable all PWM outputs. Cleared by user to disable all PWM outputs.
Rev. PrA | Page 47 of 92
ADUC7122
Table 77. PWM Output Selection
PWMCOM1 MMR ENA HOFF POINV 0 0 x x 1 x 1 0 0 1 0 0 1 0 1 1 0 1
1
Preliminary Technical Data
Table 79. PWMCON2 MMR Bit Designations
PWM Outputs PWM2 PWM3 1 1 0 1 0 HS1 1 LS 0 LS1 1 1 HS1 PWM4 1 0 LS1 0 1 LS1
DIR x x 0 1 0 1
PWM1 1 1 0 HS1 HS1 1
HS = high side, LS = low side.
On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 78). Table 78. Compare Register
Name PWM1COM1 PWM1COM2 PWM1COM3 PWM2COM1 PWM2COM2 PWM2COM3 PWM3COM1 PWM3COM2 PWM3COM3 Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W
The PWM trip interrupt can be cleared by writing any value to the PWMICLR MMR. Note that when using the PWM trip interrupt, users should make sure that the PWM interrupt has been cleared before exiting the ISR. This prevents generation of multiple interrupts.
(Address = 0xFFFF0FB4, Default Value = 0x00) Bit Value Name Description 7 CSEN Set to 1 by the user to enable the PWM to generate a convert start signal. Cleared by user to disable the PWM convert start signal. 3:0 CSD3 Convert start delay. Delays the convert start signal by a number of clock pulses. CSD2 CSD1 CSD0 0000 4 clock pulses. 0001 8 clock pulses. 0010 12 clock pulses. 0011 16 clock pulses. 0100 20 clock pulses. 0101 24 clock pulses. 0110 28 clock pulses. 0111 32 clock pulses. 1000 36 clock pulses. 1001 40 clock pulses. 1010 44 clock pulses. 1011 48 clock pulses. 1100 52 clock pulses. 1101 56 clock pulses. 1110 60 clock pulses. 1111 64 clock pulses.
PWM CONVERT START CONTROL
The PWM can be configured to generate an ADC convert start signal after the active low side signal goes high. There is a programmable delay between when the low-side signal goes high and the convert start signal is generated. This is controlled via the PWMCON2 MMR. If the delay selected is higher than the width of the PWM pulse, the interrupt remains low.
When calculating the time from the convert start delay to the start of an ADC conversion, the user needs to take account of internal delays. The example below shows the case for a delay of four clocks. One additional clock is required to pass the convert start signal to the ADC logic. Once the ADC logic receives the convert start signal an ADC conversion begins on the next ADC clock edge (see Figure 33).
UCLOCK
LOW SIDE
COUNT
PWM SIGNAL TO CONVST SIGNAL PASSED TO ADC LOGIC
06020-045
Figure 33. ADC Conversion
Rev. PrA | Page 48 of 92
Preliminary Technical Data GENERAL-PURPOSE I/O
The ADUC7122 provides 32 general-purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning that the GPIOs support an input voltage of 5 V. In general, many of the GPIO pins have multiple functions (see Table 82). By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor (of about 100 k) and their drive capability is 1.6 mA. Note that a maximum of 20 GPIO can drive 1.6 mA at the same time. The 32 GPIOs are grouped in four ports: Port 0 to Port 3. Each port is controlled by four or five MMRs, with x representing the port number. Table 80. GPxCON Register
Name GP0CON GP1CON GP2CON GP3CON Address 0xFFFF0D00 0xFFFF0D04 0xFFFF0D08 0xFFFF0D0C Default Value 0x00000000 0x00000000 0x00000000 0x11111111 Access R/W R/W R/W R/W 1
ADUC7122
Table 82. GPIO Pin Function Designations1
Port 0 Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 00 GPIO GPIO Configuration (see GPxCON) 01 10 SCL1 N/A SDA1 JTAG disabled GPIO SPICLK JTAG disabled GPIO SPIMISO SYNC GPIO SPIMOSI TRIP CONVST GPIO SPICS GPIO MRESET N/A GPIO TRST N/A GPIO SIN SCL2 GPIO SOUT SDA2 GPIO PWM1 XCLK GPIO PWM2 N/A GPIO N/A N/A GPIO N/A N/A GPIO/IRQ0 N/A N/A GPIO/IRQ1 N/A N/A GPIO N/A N/A GPIO/IRQ2 N/A N/A GPIO PWM5 N/A GPIO PWM6 N/A GPIO/IRQ3 N/A N/A GPIO N/A N/A GPIO N/A N/A GPIO N/A N/A GPIO/IRQ4 PWM3 N/A GPIO/IRQ5 PWM4 N/A GPIO N/A N/A GPIO N/A N/A GPIO N/A N/A GPIO N/A N/A 11 PLAI[5] PLAI[4] PLAO[13] PLAO[12] PLAI[11] PLAI[10] PLAI[2] PLAI[3] PLAI[7] PLAI[1] PLAI[8] PLAI[9] PLAO[5] PLAO[4] PLAI[13] PLAI[12] PLAI[1] PLAI[14] PLAO[7] PLAO[6] PLAI[15] PLAI[0] PLAO[0] PLAO[1] PLAO[2] PLAO[3] PLAO[8] PLAO[9] PLAO[10] PLAO[11]
The input level of any GPIO can be read at any time in the GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADUC7122 parts enter a power-saving mode, the GPIO pins retain their state. GPxCON is the Port x control register, and it selects the function of each pin of Port x, as described in Table 82. Table 81. GPxCON MMR Bit Designations
Bit 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Description Reserved Select function of Px.7 pin Reserved Select function of Px.6 pin Reserved Select function of Px.5 pin Reserved Select function of Px.4 pin Reserved Select function of Px.3 pin Reserved Select function of Px.2 pin Reserved Select function of Px.1 pin Reserved Select function of Px.0 pin
2
3
1
N/A means no secondary function exists.
Rev. PrA | Page 49 of 92
ADUC7122
Table 83. GPxPAR Register
Name GP0PAR GP1PAR GP2PAR GP3PAR Address 0xFFFF0D2C 0xFFFF0D3C 0xFFFF0D4C 0xFFFF0D5C Default Value 0x20000000 0x00000000 0x00000000 0x00222222 Access RW RW RW RW Name GP0SET GP1SET GP2SET GP3SET
Preliminary Technical Data
Table 87. GPxSET Register
Address 0xFFFF0D24 0xFFFF0D34 0xFFFF0D44 0xFFFF0D54 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W
GPxPAR programs the parameters for Port 0, Port 1, Port 2 and Port 3. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR. Table 84. GPxPAR MMR Bit Designations
Bit 31:29 28 27:25 24 23:21 20 19:17 16 15:13 12 11:9 8 7:5 4 3:1 0 Description Reserved Pull-up disable Px.7 pin Reserved Pull-up disable Px.6 pin Reserved Pull-up disable Px.5 pin Reserved Pull-up disable Px.4 pin Reserved Pull-up disable Px.3 pin Reserved Pull-up disable Px.2 pin Reserved Pull-up disable Px.1 pin Reserved Pull-up disable Px.0 pin
GPxSET is a data set Port x register. Table 88. GPxSET MMR Bit Designations
Bit 31: 24 23:16 Description Reserved. Data Port x Set Bit. Set to 1 by user to set bit on Port x; also sets the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data out. Reserved. Address 0xFFFF0D28 0xFFFF0D38 0xFFFF0D48 0xFFFF0D58 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W
15: 0 Name GP0CLR GP1CLR GP2CLR GP3CLR
GPxCLR Register
GPxCLR is a data clear Port x register. Table 89. GPxCLR MMR Bit Designations
Bit 31:24 23:16 Description Reserved. Data Port x Clear Bit. Set to 1 by user to clear bit on Port x; also clears the corresponding bit in the GPxDAT MMR. Cleared to 0 by user; does not affect the data out. Reserved.
Table 85. GPxDAT Register
Name GP0DAT GP1DAT GP2DAT GP3DAT Address 0xFFFF0D20 0xFFFF0D30 0xFFFF0D40 0xFFFF0D50 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access R/W R/W R/W R/W 15:0
GPxDAT is a Port x configuration and data register. It configures the direction of the GPIO pins of Port x, sets the output value for the pins configured as output, and receives and stores the input value of the pins configured as input. Table 86. GPxDAT MMR Bit Designations
Bit 31:24 Description Direction of the Data. Set to 1 by user to configure the GPIO pin as an output. Cleared to 0 by user to configure the GPIO pin as an input. Port x Data Output. Reflect the state of Port x pins at reset (read only). Port x Data Input (Read Only).
23:16 15:8 7:0
Rev. PrA | Page 50 of 92
Preliminary Technical Data
Open collector functionality is available on the following GPIO pins: P1.7, P1.6, port 2 and port 3. Table 90. GPxOCE MMR Bit Designations
Bit 31:8 7 Description Reserved. GPIO Px.7 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open collector GPIO Px.6 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.5 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.4 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.3 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.2 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.1 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector GPIO Px.0 open-collector enable Set to 1 by the user to enable open-collector Set to 0 by the user to disable open-collector
ADUC7122
6
5
4
3
2
1
0
Rev. PrA | Page 51 of 92
ADUC7122 UART SERIAL INTERFACE
The ADUC7122 features a 16450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider that facilitates high accuracy baud rate generation and a network addressable mode. The UART functionality is available on the P1.0 and P1.1 pins of the ADUC7122. The serial communication adopts an asynchronous protocol that supports various word length, stop bits, and parity generation options selectable in the configuration register.
Preliminary Technical Data
Calculation of the baud rate using fractional divider is as follows:
Baud Rate 41.78 MHz 16 DL 2 ( M N ) 2048
(2)
M
41.78 MHz N 2048 Baud Rate 16 DL 2
For example, generation of 19,200 baud M
M
41.78 MHz N 2048 19200 16 67 2
N 1.015 2048
BAUD RATE GENERATION
The ADUC7122 features two methods of generating the UART baud rate: normal 450 UART baud rate generation and ADUC7122 fractional divider.
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL). The standard baud rate generator formula is
Baud rate 41.78 MHz 16 2 DL
where: M = 1. N = 0.015 x 2048 = 30.
Baud Rate
41.78 MHz 16 67 2 1
30 2048
where Baud Rate = 19,219 bps.
(1)
UART REGISTER DEFINITION
The UART interface consists of the following ten registers: COMTX: 8-bit transmit register COMRX: 8-bit receive register COMDIV0: divisor latch (low byte) COMDIV1: divisor latch (high byte) COMCON0: line control register COMCON1: line control register COMSTA0: line status register COMIEN0: interrupt enable register COMIID0: interrupt identification register COMDIV2: 16-bit fractional baud divide register COMTX, COMRX, and COMDIV0 share the same address location. COMTX and COMRX can be accessed when Bit 7 in the COMCON0 register is cleared. COMDIV0 can be accessed when Bit 7 of COMCON0 is set.
Table 91 lists common baud rate values. Table 91. Baud Rate Using the Standard Baud Rate Generator
Baud Rate 9600 19,200 115,200 DL 0x88 0x44 0x0B Actual Baud Rate 9600 19,200 118,691 % Error 0% 0% 3%
ADUC7122 Fractional Divider
The fractional divider combined with the normal baud rate generator allows the generating of a wider range of more accurate baud rates.
CORE CLOCK /2 FBEN
/(M + N/2048)
Figure 34. Baud Rate Generation Options
06020-048
/16DL
UART
Rev. PrA | Page 52 of 92
UART TX Register
Write to this 8-bit register to transmit data using the UART. Name: Address: Access: COMTX 0xFFFF0800 Write only
UART Divisor Latch Register 1
This 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the UART operates. Name: Address: Default Value: Access: COMDIV1 0xFFFF0804 0x00 Read/write
UART RX Register
This 8-bit register is read from to receive data transmitted using the UART. Name: Address: Default Value: Access: COMRX 0xFFFF0800 0x00 Read only
UART Control Register 0
This 8-bit register controls the operation of the UART in conjunction with COMCON1. Name: Address: Default Value: Access: COMCON0 0xFFFF080C 0x00 Read/write
UART Divisor Latch Register 0
This 8-bit register contains the least significant byte of the divisor latch that controls the baud rate at which the UART operates. Name: Address: Default Value: Access: COMDIV0 0xFFFF0800 0x00 Read/write
Rev. PrA | Page 53 of 92
ADUC7122
Table 92. COMCON0 MMR Bit Designations
Bit 7 Name DLAB
Preliminary Technical Data
Description Divisor latch access. Set by user to enable access to COMDIV0 and COMDIV1 registers. Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX, and COMIEN0. Set break. Set by user to force TxD to 0. Cleared to operate in normal mode. Stick parity. Set by user to force parity to defined values. 1 if EPS = 1 and PEN = 1. 0 if EPS = 0 and PEN = 1. Even parity select bit. Set for even parity. Cleared for odd parity. Parity enable bit. Set by user to transmit and check the parity bit. Cleared by user for no parity transmission or checking. Stop bit. Set by the user to transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length is 6, 7, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by the user to generate one stop bit in the transmitted data. Word length select. 00 = 5 bits. 01 = 6 bits. 10 = 7 bits. 11 = 8 bits.
6
BRK
5
SP
4
EPS
3
PEN
2
STOP
1 to 0
WLS
UART Control Register 1
This 8-bit register controls the operation of the UART in conjunction with COMCON0. Name: Address: Default Value: Access: COMCON1 0xFFFF0810 0x00 Read/write
Table 93. COMCON1 MMR Bit Designations
Bit 7:5 4 Name LOOPBACK Description Reserved bits. Not used. Loopback. Set by user to enable loopback mode. In loopback mode, the TxD is forced high. Reserved bits. Not used. Request to send. Set by user to force the RTS output to 0. Cleared by user to force the RTS output to 1. Data Terminal Ready. Set by user to force the DTR output to 0. Cleared by user to force the DTR output to 1.
3:2 1
RTS
0
DTR
Rev. PrA | Page 54 of 92
ADUC7122
UART Status Register 0
Name: Address: Default Value: Access: Function: COMSTA0 0xFFFF0714 0x60 Read only This 8-bit read-only register reflects the current status on the UART.
Preliminary Technical Data
Table 94. COMSTA0 MMR Bit Designations
Bit 7 6 Name TEMT Description Reserved. COMTX and shift register empty status bit. Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been transmitted, that is, no more data is present in the shift register. Cleared automatically when writing to COMTX. COMTX empty status bit. Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set, the previous data might not have been transmitted yet and can still be present in the shift register. Cleared automatically when writing to COMTX. Break indicator. Set when SIN is held low for more than the maximum word length. Cleared automatically. Framing error. Set when the stop bit is invalid. Cleared automatically. Parity error. Set when a parity error occurs. Cleared automatically. Overrun error. Set automatically if data are overwritten before being read. Cleared automatically. Data ready. Set automatically when COMRX is full. Cleared by reading COMRX.
5
THRE
4
BI
3
FE
2
PE
1
OE
0
DR
Rev. PrA | Page 55 of 92
ADUC7122
UART Interrupt Enable Register 0
Name: Address: Default value: Access: Function: COMIEN0 0xFFFF0804 0x00 Read/write The 8-bit register enables and disables the individual UART interrupt sources.
10 0 Bits[2:1] Status Bits 00 11
Preliminary Technical Data
Table 96. COMIID0 MMR Bit Designations
Bit 0 NINT 1 0 Clearing Operation Read COMSTA0 Read COMRX
Priority 1
2
Table 95. COMIEN0 MMR Bit Designations
Bit 7:4 3 Name EDSSI Description Reserved. Not used. Modem Status Interrupt Enable Bit. Set by user to enable generation of an interrupt if any of COMSTA0[3:1] are set. Cleared by user. RxD Status Interrupt Enable Bit. Set by the user to enable generation of an interrupt if any of the COMSTA0[3:1] register bits are set. Cleared by the user. Enable Transmit Buffer Empty Interrupt. Set by the user to enable an interrupt when the buffer is empty during a transmission, that is, when COMSTA[5] is set. Cleared by the user. Enable Receive Buffer Full Interrupt. Set by the user to enable an interrupt when the buffer is full during a reception. Cleared by the user.
01
0
3
00
0
4
Definition No interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt
Write data to COMTX or read COMIID0 Read COMSTA1 register
UART Fractional Divider Register
This 16-bit register controls the operation of the fractional divider for the ADUC7122. Name: Address: Default value: Access: COMDIV2 0xFFFF082C 0x0000 Read/write
2
ELSI
1
ETBEI
0
ERBFI
Table 97. COMDIV2 MMR Bit Designations
Bit 15 Name FBEN Description Fractional Baud Rate Generator Enable Bit. Set by the user to enable the fractional baud rate generator. Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator. Reserved. M. If FBM = 0, M = 4. See Equation 2 for the calculation of the baud rate using a fractional divider and table 76 for common baud rate values. N. See Equation 2 for the calculation of the baud rate using a fractional divider and table 76 for common baud rate values.
UART Interrupt Identification Register 0
Name: Address: Default value: Access: Function: COMIID0 0xFFFF0808 0x01 Read only This 8-bit register reflects the source of the UART interrupt.
10:0 FBN[10:0] 14:13 12:11
FBM[1:0]
Rev. PrA | Page 56 of 92
Preliminary Technical Data I2C
The ADUC7122 incorporates two I2C peripherals that can be separately configured as a fully I2C compatible I2C bus Master device or, as a fully I2C bus compatible slave device. Because both peripherals are identical, only one is explained here. The two pins used for data transfer, SDA and SCL, are configured in a wired-AND format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up values are between 4.7 k and 10 k. The I2C bus peripheral's address in the I2C bus system is programmed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (Read or /Write) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. The I2C peripheral can only be configured as a master or slave at any given time. The same I2C channel cannot simultaneously support master and slave modes. The I2C interface on the ADUC7122 includes the following features: Support for Repeated Start Conditions. In Master mode, the ADUC7122 can be programmed to generate a Repeated Start. In Slave mode, the ADUC7122 recognizes Repeated Start conditions. In Master and Slave mode, the part recognizes both 7-bit and 10-bit bus addresses. In I2C Master mode, the ADUC7122 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence. Clock stretching is supported in both Master and Slave modes. In Slave mode, the ADUC7122 can be programmed to return a "NACK." This allows the validiation of checksum bytes at the end of I2C transfers. Bus arbitration in Master mode is supported. Internal and external loopback modes are supported for I2C hardware testing. In loopback mode. The Transmit and receive circuits in both Master and Slave mode contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs.
ADUC7122
Configuring External pins for I2C functionality
The I2C pins of the ADUC7122 device are P0.0 and P0.1 for I2C1, and P1.0 and P1.1 for I2C2. P0.0 and P1.0 are the I2C clock signals and P0.1 and P1.1 are the I2C data signals. For instance, to configure the I2C1 pins (SCL1, SDA1), Bit 0 and Bit 4 of the GP0CON register must be set to 1 to enable I2C mode. Alternatively, to configure the I2C2 pins (SCL2, SDA2), Bit 1 and Bit 5 of the GP0CON register must be set to 1 to enable I2C mode.
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CxDIV MMR as follows:
f SERIAL CLOCK fUCLK (2 DIVH ) (2 DIVL)
where: fUCLK = clock before the clock divider. DIVH = the high period of the clock. DIVL = the low period of the clock. Thus, for 100 kHz operation DIVH = DIVL = 0xCF and for 400 kHz DIVH = 0x28, DIVL = 0x3C The I2CxDIV register corresponds to DIVH:DIVL
I2C BUS ADDRESSES
Slave Mode
In slave mode, the registers I2CID0, I2CID1, I2CID2, and I2CID3 contain the device IDs. The device compares the four I2CIDx registers to the address byte received from the bus Master. To be correctly addressed, the 7 MSBs of either ID register must be identical to that of the 7 MSBs of the first received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The ADUC7122 also supports 10-bit addressing mode. When Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit address is supported in slave mode and is stored in registers I2CID0 and I2CID1. The 10-bit address is derived as follows: I2CID0[0] is the read/write bit and is not part of the I2C address. I2CID0[7:1] = Address Bits[6:0]. I2CID1[2:0] = Address Bits[9:7]. I2CID1[7:3] must be set to 11110b

Rev. PrA | Page 57 of 92
ADUC7122
Master Mode
In master mode, the I2CADR0 register is programmed with the I2C address of the device. In 7-bit address mode, I2CADR0[7:1] are set to the device address. I2CADR0[0] is the read/write bit. In 10-bit address mode, the 10-bit address is created as follows: I2CADR0[7:3] must be set to 11110b. I2CADR0[2:1] = Address Bits[9:8]. I2CADR1[7:0] = Address Bits[7:0]. I2CADR0[0] is the read/write bit.
Preliminary Technical Data
I2C Master Registers I2C Master Control Register
Name: Address: Default value: Access: Function: I2C0MCTL, I2C1MCTL 0xFFFF0880, 0xFFFF0900 0x0000, 0x0000 Read/write This 16-bit MMR configures I2C peripheral in master mode.
I2C REGISTERS
The I2C peripheral interfaces consists of a number of MMRs. These are described in the following section.
Table 98. I2CxMCTL MMR Bit Designations
Bit 15:9 8 Name I2CMCENI Description Reserved. These bits are reserved and should not be written to I2C transmission complete Interrupt Enable bit Set this bit to enable an interrupt on detecting a Stop condition on the I2C bus. Clear this interrupt source. I2C NACK received Interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a NACK. Clear this interrupt source. I2C Arbitration lost Interrupt Enable bit.. Set this bit to enable interrupts when the I2C master has lost in trying to gain control of the I2C bus. Clear this interrupt source. I2C Transmit Interrupt Enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte Clear this interrupt source. I2C Receive Interrupt Enable bit. Set this bit to enable interrupts when the I2C master receives data Cleared by user to disable interrupts when the I2C master is receiving data I2C Master SCL stretch Enable bit. Set this bit to 1 to enable Clock stretching. When SCL is low, setting this bit will force the device to hold SCL low until I2CMSEN is cleared. If SCL is high, setting this bit will force the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. I2C Internal Loopback Enable Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their Respective input signals. Cleared by user to disable Loopback mode. I2C Master Backoff Disable bit Set this bit to allow the device to compete for control of the bus even if another device is currently driving a Start Condition Clear this bit to back off until the I2C bus becomes free. I2C Master Enable bit. Set by user to enable I2C Master mode. Cleared disable I2C Master mode.
7
I2CNACKENI
6
I2CALENI
5
I2CMTENI
4
I2CMRENI
3
I2CMSEN
2
I2CILEN
1
I2CBD
0
I2CMEN
Rev. PrA | Page 58 of 92
Preliminary Technical Data
I2C Master Status Register
Name: Address: Default value: Access: Function: I2C0MSTA , I2C1MSTA 0xFFFF0884, 0xFFFF0904 0x0000, 0x0000 Read This 16-bit MMR is I2C status register in master mode.
ADUC7122
Table 99 I2CxMSTA MMR Bit Designations
Bit 15:11 10 Name I2CBBUSY Description Reserved. These bits are reserved. I2C bus busy status bit. This bit is set to 1 when a Start condition is detected on the I2C bus. This bit is cleared when a Stop condition is detected on the bus Master Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit will be cleared in all other conditions. I2C transmission complete status bit. This bit is set to 1 when a transmission is complete between the Master and the Slave it was communicating with. If the I2CMCENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set. Clear this interrupt source. I2C master NACK data bit This bit will be set to 1 when a NACK condition is received by the Master in response to a Data write transfer. If the I2CNACKENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set. This bit will be cleared in all other conditions. I2C master busy status bit Set to 1 when the Master is busy processing a transaction. Cleared if the Master is ready or if another Master device has control of the bus I2C arbitration lost status bit.. This bit is set to 1 when the I2C master has lost in trying to gain control of the I2C bus. If the I2CALENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set. This bit will be cleared in all other conditions. I2C master NACK address bit This bit will be set to 1 when a NACK condition is received by the Master in response to an Address. If the I2CNACKENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set. This bit will be cleared in all other conditions. I2C master receive request bit This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCTL is set, an interrupt will be generated. This bit will be cleared in all other conditions. I2C master transmit request bit This bit will go high if the Tx FIFO is empty or only contains 1 byte and the master has transmitted an address + write. If the I2CMTENI bit in I2CxMCTL is set, an interrupt will be generated when this bit is set. This bit will be cleared in all other conditions. I2C master Tx FIFO status bits. 00 = I2C master Tx FIFO empty 01 = 1 byte in master Tx FIFO 10 = 1 byte in master Tx FIFO 11 = I2C Master Tx FIFO Full.
9
I2CMRxFO
8
I2CMTC
7
I2CMNA
6
I2CMBUSY
5
I2CAL
4
I2CMNA
3
I2CMRXQ
2
I2CMTXQ
1:0
I2CMTFSTA
Rev. PrA | Page 59 of 92
ADUC7122
I2C Master Receive Register
Name: Address: Default Value: Access: Function: I2C0MRX , I2C1MRX 0xFFFF0888, 0xFFFF0908 0x00, 0x00 Read only This 8-bit MMR is the I2C master receive register. Name: Address: Default Value: Access: Function:
Preliminary Technical Data
I2C Master Read Count Register
I2C0MCNT0, I2C1MCNT0 0xFFFF0890, 0xFFFF0910 0x0000, 0x0000 Read/write This 16-bit MMR holds the required number of bytes when the master begins a read sequence from a slave device.
I2C Master Transmit Register
Name: Address: Default Value: Access: Function: I2C0MTX, I2C1MTX 0xFFFF088C 0xFFFF090C 0x00, 0x00 Write only This 8-bit MMR is the I2C master transmit register. Name: Address: Default value: Access: Function:
I2C Master Current Read Count Register
I2C0MCNT1I2C1MCNT1 0xFFFF0894, 0xFFFF0914 0x00, 0x00 Read This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device.
Table 100. I2CxMCNT0 MMR Bit Descriptions (Address = 0xFFFF0890, 0xFFFF0910, Default value = 0x0000)
Bit 15:9 8 7:0 Name I2CRECNT I2CRCNT Description Reserved. Set this bit if greater than 256 bytes are required from the slave. Clear this bit when reading 256 bytes or less. These 8 bits hold the number of bytes required during a slave read sequence, minus 1. If only a single byte is required, these bits should be set to 0.
Rev. PrA | Page 60 of 92
Preliminary Technical Data
I2C Address 0 Register
Name: Address: Default value: Access: Function: I2C0ADR0, I2C1ADR0 0xFFFF0898, 0xFFFF0918 0x00, 0x00 Read/write This 8-bit MMR holds the 7-bit slave address + the read/write bit when the master begins communicating with a slave.
ADUC7122
I2C Master Clock Control Register
Name: Address: Default Value: Access: Function: I2C0DIV, I2C1DIV 0xFFFF08A4, 0xFFFF0924 0x1F1F, 0x1F1F Read/write This MMR controls the frequency of the I2C clock generated by the master on to the SCL pin. For further details, see I2C initial section.
I2C Address 1 Register
Name: Address: Default value: Access: Function: I2C0ADR1, I2C1ADR1 0xFFFF089C , 0xFFFF091C 0x00, 0x00 Read/write This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address.
Table 101. I2CxADR0 MMR in 7-Bit Address Mode (Address = 0xFFFF0898, 0xFFFF0918, Default Value = 0x00)
Bit 7:1 0 Name I2CADR R/W Description These bits contain the 7-bit address of the required slave device. Bit 0 is the read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested.
Table 102. I2CxADR0 MMR in 10-Bit Address Mode
Bit 7:3 2:1 0 Name I2CMADR R/W Description These bits must be set to [11110b] in 10-bit address mode. These bits contain ADDR[9:8] in 10-bit addressing mode. Read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested.
Table 103. I2CxADR1 MMR in 10-Bit Address Mode
Bit 7:0 Name I2CLADR Description These bits contain ADDR[7:0] in 10-bit addressing mode.
Table 104. I2CxDIV MMR
Bit 15:8 7:0 Name DIVH DIVL Description These bits control the duration of the High period of SCL. These bits control the duration of the low period of SCL.
Rev. PrA | Page 61 of 92
ADUC7122
I2C Slave Registers I2C Slave Control Register
Name: Address: Default Value: Access: Function: I2C0SCTL, I2C1SCTL 0xFFFF08A8, 0xFFFF0928 0x0000, 0x000 Read/write This 16-bit MMR configures the I2C peripheral in slave mode.
Preliminary Technical Data
Table 105. I2CxSCTL MMR Bit Designations
Bit 15:11 10 Name I2CSTXENI Description Reserved bits. Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. Slave receive interrupt enable bit. Set this bit to enable an interrupt after the Slave receives data. Clear this interrupt source. I2C stop condition detected interrupt enable bit Set this bit to enable an interrupt on detecting a Stop condition on the I2C bus. Clear this interrupt source. I2C NACK enable bit. Set this bit to NACK the next byte in the transmission sequence. Clear this bit to let the Hardware control the ACK/NACK sequence. I2C slave SCL stretch enable bit. Set this bit to 1 to enable Clock stretching. When SCL is low, setting this bit will force the device to hold SCL low until I2CSSEN is cleared. If SCL is high, setting this bit will force the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. I2C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit Transmission. Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the Read bit Transmission. I2C general call status and ID clear bit. Writing a 1 to this bit will clear the general call status and ID bits in the I2CxSSTA register. Clear this bit at all other times. I2C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a "to whom it may concern" call. The ADUC7122 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be written to 1, as per the I2C January 2000 bus specification. Set this bit and I2CGCEN to enable Hardware General call recognition in Slave mode. Clear to disable recognition of Hardware General Call commands.
9
I2CSRXENI
8
I2CSSENI
7
I2CNACKEN
6
I2CSSEN
5
I2CSETEN
4
I2CGCCLR
3
I2CHGCEN
Rev. PrA | Page 62 of 92
Preliminary Technical Data
Bit 2 Name I2CGCEN
ADUC7122
1 0
Reserved I2CSEN
Description I2C general call enable. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. Set this bit to allow the Slave "ACK" I2C General Call commands. Clear to disable recognition of General Call commands. Always set this bit = 0. I2C slave enable bit. Set by user to enable I2C slave mode. Clear to disable I2Cslave mode.
I2C Slave Status Registers
Name: Address: Default Value: Access: Function: I2C0SSTA, I2C1SSTA 0xFFFF08AC, 0xFFFF092C 0x0000, 0x0000 Read/write This 16-bit MMR is the I2C status register in slave mode.
Table 106. I2CxSSTA MMR Bit Designations
Bit 15 14 Name I2CSTA Description Reserved bit. This bit is set to 1 if: A start condition followed by a matching address is detected. It is also set if a start byte (0x01) is received. If general calls are enabled and a general call code of 0x00 is received. This bit is cleared on receiving a stop condition This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition I2C Address matching register. These bits indicate which I2CxIDx register matches the received address. 00 = received address matches I2CxID0 01 = received address matches I2CxID1 10 = received address matches I2CxID2 11 = received address matches I2CxID3 I2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CxSCTL is set, an interrupt is generated. This bit is cleared by reading this register. I2C general call ID bits 00 = no general call received. 01 = general call reset and program address. 10 = general program address. 11 = general call matching alternative ID Note that these bits are not cleared by a general call reset command. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCTL.
13 12-11
I2CREPS I2CID[1:0]
10
I2CSS
9:8
I2CGCID[1:0]
Rev. PrA | Page 63 of 92
ADUC7122
Bit 7 Name I2CGC
Preliminary Technical Data
Description I2C general call status bit This bit is set to 1 if the slave receives a general call command of any type. If the command received was a reset command, then all registers will return to their default state. If the command received was a hardware general call, the Rx FIFO holds the 2nd byte of the command and this can be compared with the I2CxALT register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCTL. I2C slave busy status bit Set to 1 when the slave receives a start condition Cleared by hardware if: The received address does not match any of the I2CxIDx registers The slave device receives a stop condition. If a repeated start address does not match any of the I2CxIDx registers I2C slave NACK data bit This bit is set to 1 when the slave responded to a bus address with a NACK. This bit is asserted under the following conditions: If NACK was returned because there was no data in the Tx FIFO If the I2CNACKEN bit was set in the I2CxSCTL register. This bit is cleared in all other conditions. Slave Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. I2C slave receive request bit This bit is set to 1 when the slave's Rx FIFO is not empty. This bit causes an interrupt to occur if the I2CSRXENI bit in I2CxSCTL is set. The Rx FIFO must be read or flushed to clear this bit I2C slave transmit request bit This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set. This bit is cleared in all other conditions. I2C slave FIFO underflow status bit. This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. I2C slave early transmit FIFO status bit If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high of the slave Tx FIFO is empty. If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read.
6
I2CSBUSY
5
I2CSNA
4
I2CSRxFO
3
I2CSRXQ
2
I2CSTXQ
1
I2CSTFE
0
I2CETSTA
Rev. PrA | Page 64 of 92
Preliminary Technical Data
I2C Slave Receive Registers
Name: Address: Default value: Access: Function: I2C0SRX, I2C1SRX 0xFFFF08B0, 0xFFFF0930 0x00 Read This 8-bit MMR is the I2C slave receive register.
ADUC7122
I2C Slave Device ID Registers
Name: Addresses: I2C0IDx, I2C1IDx 0xFFFF093C = I2C1ID0 0xFFFF08BC = I2C0ID0 0xFFFF0940 = I2C1ID1 0xFFFF08C0 = I2C0ID1 0xFFFF0944 = I2C1ID2 0xFFFF08C4 = I2C0ID2 0xFFFF0948 = I2C1ID3 0xFFFF08C8 = I2C0ID3 Default value: Access: Function: 0x00 Read/write These 8-bit MMRs are programmed with I2C bus IDs of the slave. See the I2C Bus Addresses section for further details.
I2C Slave Transmit Registers
Name: Address: Default value: Access: Function: I2C0STX, I2C1STX 0xFFFF08B4, 0xFFFF0934 0x00 Write This 8-bit MMR is the I2C slave transmit register.
I2C Hardware General Call Recognition Registers
Name: Address: Default value: Access: Function: I2C0ALT, I2C1ALT 0xFFFF08B8, 0xFFFF0938 0x00 Read/write This 8-bit MMR is used with hardware general calls when I2CxSCTL bit 3 is set to 1. This register is used in cases where a master is unable to generate an address for a slave, and instead, the slave must generate the address for the master.
Rev. PrA | Page 65 of 92
ADUC7122
I2C COMMON REGISTERS
I2C FIFO Status Register
Name: Address: Default value: Access: Function: I2C0FSTA, I2C1FSTA 0xFFFF08CC, 0xFFFF094C 0x0000 Read/write
Preliminary Technical Data
These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes.
Table 107. I2CxFSTA MMR Bit Designations
Bit 15:10 9 8 7:6 Name I2CFMTX I2CFSTX I2CMRXSTA Description Reserved bits. Set this bit to 1 to flush the master, Tx FIFO. Set this bit to 1 to flush the slave, Tx FIFO. I2C master receive FIFO status bits. 00 = FIFO empty. 01 = byte written to FIFO. 10 = 1 byte in FIFO. 11 = FIFO full. I2C master transmit FIFO status bits. 00 = FIFO empty. 01 = byte written to FIFO. 10 = 1 byte in FIFO. 11 = FIFO full. I2C slave receive FIFO status bits. 00 = FIFO empty 01 = byte written to FIFO 10 = 1 byte in FIFO 11 = FIFO full I2C slave transmit FIFO status bits. 00 = FIFO empty. 01 = byte written to FIFO. 10 = 1 byte in FIFO. 11 = FIFO full.
5:4
I2CMTXSTA
3:2
I2CSRXSTA
1:0
I2CSTXSTA
Rev. PrA | Page 66 of 92
Preliminary Technical Data SERIAL PERIPHERAL INTERFACE
The ADUC7122 integrates a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 20 Mb. The SPI port can be configured for master or slave operation and typically consists of four pins: SPIMISO, SPIMOSI, SPICLK, and SPI CS.
ADUC7122
SPI CHIP SELECT (SPI CS INPUT) PIN
In SPI slave mode, a transfer is initiated by the assertion of SPI CS, which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by deassertion of SPI CS. In slave mode, SPI CS is always an input. In SPI master mode, the SPICS is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon completion.
SPIMISO (MASTER IN, SLAVE OUT) PIN
The SPIMISO pin is configured as an input line in master mode and an output line in slave mode. The SPIMISO line on the master (data in) should be connected to the SPIMISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first.
CONFIGURING EXTERNAL PINS FOR SPI FUNCTIONALITY
The SPI pins of the ADUC7122 device are P0[2..4]. P0.5 is the Slave Chip Select pin. In Slave mode, this pin is an input and must be driven low by the Master. In Master mode, this pin is an output and will go low at the beginning of a transfer and high at the end of a transfer. P0.2 is the SPICLK pin. P0.3 is the master in, slave out (SPIMISO) pin. P0.4 is the master out, slave in (SPIMOSI) pin. To configure P0[2:4] for SPI mode, see the General-Purpose I/O section.
SPIMOSI (MASTER OUT, SLAVE IN) PIN
The SPIMOSI pin is configured as an output line in master mode and an input line in slave mode. The SPIMOSI line on the master (data out) should be connected to the SPIMOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first.
SPICLK (SERIAL CLOCK I/O) PIN
The master serial clock (SPICLK) synchronizes the data being transmitted and received through the MOSI SPICLK period. Therefore, a byte is transmitted/received after eight SPICLK periods. The SPICLK pin is configured as an output in master mode and as an input in slave mode. In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the SPIDIV register as follows:
f SERIAL CLOCK
f UCLK 2 (1 SPIDIV)
The maximum speed of the SPI clock is independent on the clock divider bits. In Slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 10 Mb. In both master and slave modes, data is transmitted on one edge of the SPICLK signal and sampled on the other. Therefore, it is important that the polarity and phase are configured the same for the master and slave devices.
Rev. PrA | Page 67 of 92
ADUC7122
SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. Name: Address: Default value: Access: Function:
Table 108. SPISTA MMR Bit Designations
Bit 15:12 11 Name SPIREX
Preliminary Technical Data
SPI Status Register
SPISTA 0xFFFF0A00 0x0000 Read/write This 16-bit MMR contains the status of the SPI interface in both master and slave modes.
10:8
SPIRXFSTA[2:0]
7
SPIFOF
6
SPIRXIRQ
5
SPITXIRQ
4
SPITXUF
3:1
SPITXFSTA[2:0]
0
SPIISTA
Description Reserved bits. SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIRXMDE. SPI Rx FIFO status bits. 000 = Rx FIFO is empty 001 = 1 valid byte in the FIFO 010 = 2 valid bytes in the FIFO 011 = 3 valid bytes in the FIFO 100 = 4 valid bytes in the FIFO Clear this bit to disable clock stretching. SPI Rx FIFO overflow status bit. Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. SPI Rx IRQ status bit. Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number of bytes have been received. Cleared when the SPISTA register is read. SPI Tx IRQ status bit. Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of bytes have been transmitted. Cleared when the SPISTA register is read. SPI Tx FIFO underflow. This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. SPI Tx FIFO status bits. 000 = Tx FIFO is empty. 001 = 1 valid byte in the FIFO. 010 = 2 valid bytes in the FIFO. 011 = 3 valid bytes in the FIFO. 100 = 4 valid bytes in the FIFO. Clear this bit to enable 7-bit address mode SPI interrupt status bit. Set to 1 when an SPI-based interrupt occurs. Cleared after reading SPISTA.
Rev. PrA | Page 68 of 92
ADUC7122
SPIRX Register
Name: Address: Default value: Access: Function: SPIRX 0xFFFF0A04 0x00 Read This 8-bit MMR is the SPI receive register.
Preliminary Technical Data
SPIDIV Register
Name: Address: Default value: Access: Function: SPIDIV 0xFFFF0A0C 0x1B Write This 8-bit MMR is the SPI baud rate selection register.
SPITX Register
Name: Address: Default value: Access: Function: SPITX 0xFFFF0A08 0x00 Write This 8-bit MMR is the SPI transmit register.
SPI Control Register
Name: Address: Default value: Access: Function: SPICON 0xFFFF0A10 0x0000 Read/write This 16-bit MMR configures the SPI peripheral in both master and slave modes.
Table 109. SPICON MMR Bit Designations
Bit 15:14 Name SPIMDE Description SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. 00 = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been received by the FIFO. 01 = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been received by the FIFO. 10 = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have been received by the FIFO. 11 = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or four bytes present SPI Tx FIFO flush enable bit. Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. Any writes to the Tx FIFO are ignored while this bit is set. Clear this bit to disable Tx FIFO flushing. SPI Rx FIFO flush enable bit. Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set all incoming data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer. Clear this bit to disable Rx FIFO flushing. Continuous transfer enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle. Loop back enable bit. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is clear.
13
SPITFLH
12
SPIRFLH
11
SPICONT
10
SPILP
9
SPIOEN
Rev. PrA | Page 69 of 92
ADUC7122
Bit 8 Name SPIROW
Preliminary Technical Data
Description SPIRX overflow overwrite enable. Set by user, the valid data in the Rx register is overwritten by the new serial byte received. Cleared by user, the new serial byte received is discarded. SPI transmit zeros when Tx FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO. SPI transfer and interrupt mode. Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full. LSB first transfer enable bit. Set by user, the LSB is transmitted first Cleared by user, the MSB is transmitted first. SPI wired or mode enable bit Set to 1 to enable open-drain data output enable. External pull-ups required on data out pins. Clear for normal output levels.. Serial clock polarity mode bit. Set by user, the serial clock idles high Cleared by user, the serial clock idles low. Serial clock phase mode bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer. Master mode enable bit Set by user to enable master mode Cleared by user to enable slave mode SPI enable bit. Set by user to enable the SPI. Cleared by user to disable the SPI.
7
SPIZEN
6
SPITMDE
5
SPILF
4
SPIWOM
3
SPICPO
2
SPICPH
1
SPIMEN
0
SPIEN
Rev. PrA | Page 70 of 92
ADUC7122 PROGRAMMABLE LOGIC ARRAY (PLA)
The ADUC7122 integrates a fully programmable logic array (PLA) that consists of two, independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements. Each PLA element contains a two-input look-up table that can be configured to generate any logic output function based on two inputs and a flip-flop. This is represented in Figure 35.
0 2 A LOOK-UP TABLE 3 1
04955-033
Preliminary Technical Data
Table 111. PLAELMx Registers
Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 Address 0xFFFF0B00 0xFFFF0B04 0xFFFF0B08 0xFFFF0B0C 0xFFFF0B10 0xFFFF0B14 0xFFFF0B18 0xFFFF0B1C 0xFFFF0B20 0xFFFF0B24 0xFFFF0B28 0xFFFF0B2C 0xFFFF0B30 0xFFFF0B34 0xFFFF0B38 0xFFFF0B3C Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
4
B
Figure 35. PLA Element
In total, 32 GPIO pins are available on each ADUC7122 for the PLA. These include 16 input pins and 16 output pins, which need to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins. The PLA is configured via a set of user MMRs. The output(s) of the PLA can be routed to the internal interrupt system, to the CONVSTART signal of the ADC, to an MMR, or to any of the 16 PLA output pins. The two blocks can be interconnected as follows: Output of Element 15 (Block 1) can be fed back to Input 0 of Mux 0 of Element 0 (Block 0) Output of Element 7 (Block 0) can be fed back to the Input 0 of Mux 0 of Element 8 (Block 1)
PLAELMx are Element 0 to Element 15 control registers. They configure the input and output mux of each element, select the function in the look-up table, and bypass/use the flip-flop. See Table 112 and Table 117.
Table 112. PLAELMx MMR Bit Descriptions
Bit 31:11 10:9 8:7 6 Value Description Reserved. Mux 0 control (see Table 117). Mux 1 control (see Table 117). Mux 2 control. Set by user to select the output of Mux 0. Cleared by user to select the bit value from PLADIN. Mux 3 control. Set by user to select the input pin of the particular element. Cleared by user to select the output of Mux 1. Look-up table control. 0. NOR. B AND NOT A. NOT A. A AND NOT B. NOT B. EXOR. NAND. AND. EXNOR. B. NOT A OR B. A. A OR NOT B. OR. 1. Mux 4 Control. Set by user to bypass the flipflop. Cleared by user to select the flip-flop (cleared by default).
5
4:1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0
Table 110. Element Input/Output
Element 0 1 2 3 4 5 6 7 PLA Block 0 Input P2.7 P2.2 P0.6 P0.7 P0.1 P0.0 P1.1 P1.0 Output P3.0 P3.1 P3.2 P3.3 P1.7 P1.6 P2.5 P2.4 Element 8 9 10 11 12 13 14 15 PLA Block 1 Input P1.4 P1.5 P0.5 P0.4 P2.1 P2.0 P2.3 P2.6 Output P3.4 P3.5 P3.6 P3.7 P0.3 P0.2 P1.3 P1.2
PLA MMRs Interface The PLA peripheral interface consists of the 21 MMRs described in the following sections.
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ADUC7122
Table 113. PLACLK Register
Name PLACLK Address 0xFFFF0B40 Default Value 0x00 Access R/W Name PLAIRQ
Preliminary Technical Data
Table 115. PLAIRQ Register
Address 0xFFFF0B44 Default Value 0x00000000 Access R/W
PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 44 MHz.
Table 114. PLACLK MMR Bit Descriptions
Bit 7 6:4 Value Description Reserved. Block 1 clock source selection. GPIO clock on P0.5. GPIO clock on P0.0. GPIO clock on P0.7. HCLK. External crystal (OCLK) (32.768 kHz). Timer1 overflow. Reserved. Reserved. Block 0 clock source selection. GPIO clock on P0.5. GPIO clock on P0.0. GPIO clock on P0.7. HCLK. External crystal (OCLK) (32.768 kHz). Timer1 overflow. Reserved.
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of the IRQ.
Table 116. PLAIRQ MMR Bit Descriptions
Bit 15:13 12 Value Description Reserved. PLA IRQ1 enable bit. Set by user to enable IRQ1 output from PLA. Cleared by user to disable IRQ1 output from PLA. PLA IRQ1 source. PLA Element 0. PLA Element 1. PLA Element 15. Reserved. PLA IRQ0 enable bit. Set by user to enable IRQ0 output from PLA. Cleared by user to disable IRQ0 output from PLA. PLA IRQ0 source. PLA Element 0. PLA Element 1. PLA Element 15.
000 001 010 011 100 101 Other 3 2:0 000 001 010 011 100 101 Other
11:8 0000 0001 1111 7:5 4
3:0 0000 0001 1111
Table 117. Feedback Configuration
Bit 10:9 Value 00 01 10 11 00 01 10 11 PLAELM0 Element 15 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 PLAELM1 to PLAELM7 Element 0 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 PLAELM8 Element 7 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15 PLAELM9 to PLAELM15 Element 8 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15
8:7
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Preliminary Technical Data
PLAADC Register
Name PLAADC Address 0xFFFF0B48 Default Value 0x00000000 Access R/W
ADUC7122
types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ). All the interrupts can be masked separately. The control and configuration of the interrupt system is managed through a number of interrupt-related registers. The bits in each IRQ and FIQ register represent the same interrupt source as described in Table 121. The ADUC7122 contains a vectored interrupt controller (VIC) that supports nested interrupts up to eight levels. The VIC also allows the programmer to assign priority levels to all interrupt sources. Interrupt nesting needs to be enabled by setting the ENIRQN bit in the IRQCONN register. A number of extra MMRs are used when the full vectored interrupt controller is enabled. IRQSTA/FIQSTA should be saved immediately upon entering the interrupt service routine (ISR) to ensure that all valid interrupt sources are serviced.
Table 121. IRQ/FIQ MMRs Bit Designations
PLAADC is the PLA source for the ADC start conversion signal.
Table 118. PLAADC MMR Bit Descriptions
Bit 31:5 4 Value Description Reserved. ADC start conversion enable bit. Set by user to enable ADC start conversion from PLA. Cleared by user to disable ADC start conversion from PLA. ADC start conversion source. PLA Element 0. PLA Element 1. PLA Element 15.
3:0 0000 0001 1111
PLADIN Register
Name PLADIN Address 0xFFFF0B4C Default Value 0x00000000 Access R/W
Bit 0 1 2 3 4 5
PLADIN is a data input MMR for PLA.
Table 119. PLADIN MMR Bit Descriptions
Bit 31:16 15:0 Description Reserved. Input bit to Element 15 to Element 0.
Description All interrupts OR'ed (FIQ only) Software Interrupt Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Timer4 Reserved PSM Undefined Flash Control 0 Flash Control 1 ADC UART SPI I2C 0 Master IRQ I2C 0 Slave IRQ I2C 1 Master IRQ I2C 1 Slave IRQ XIRQ0 (GPIO IRQ0 ) XIRQ1 (GPIO IRQ1) XIRQ2 (GPIO IRQ2 ) XIRQ3 (GPIO IRQ3) PWM XIRQ4 (GPIO IRQ4 ) XIRQ5 (GPIO IRQ5) PLA IRQ0 PLA IRQ1
Comments This bit is set if any FIQ is active User programmable interrupt source General-Purpose Timer 0 General-Purpose Timer 1 General-Purpose Timer 2 or wake-up timer General-Purpose Timer 3 or watchdog timer General-Purpose Timer 4 Reserved Power Supply Monitor This bit is not used Flash controller for Block 0 interrupt Flash controller for Block 1 interrupt ADC interrupt source bit UART interrupt source bit SPI interrupt source bit I2C master interrupt source bit I2C slave interrupt source bit I2C master interrupt source bit I2C slave interrupt source bit External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 PWM Trip interrupt source bit External Interrupt 4 External Interrupt 5 PLA block 0 IRQ bit PLA block 1 IRQ bit
PLADOUT Register
Name PLADOUT Address 0xFFFF0B50 Default Value 0x00000000 Access R
PLADOUT is a data output MMR for PLA. This register is always updated.
Table 120. PLADOUT MMR Bit Descriptions
Bit 31:16 15:0 Description Reserved. Output bit from Element 15 to Element 0.
PLALCK Register
Name PLALCK Address 0xFFFF0B54 Default Value 0x00 Access W
PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modifying any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA.
INTERRUPT SYSTEM
There are 27 interrupt sources on the ADUC7122 that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI) which is programmable by the user. The ARM7TDMI CPU core only recognizes interrupts as one of two
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
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ADUC7122
IRQ
The IRQ is the exception signal to enter the IRQ mode of the processor. It services general-purpose interrupt handling of internal and external events. All 32 bits are logically OR'ed to create a single IRQ signal to the ARM7TDMI core. The four 32-bit registers dedicated to IRQ follow.
Preliminary Technical Data
IRQSTA
IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine.
IRQSIG
IRQSIG reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read only.
IRQSIG Register
Name: Address: Default value: Access: IRQSTA 0xFFFF0000 0x00000000 Read only
IRQSIG Register
Name: Address: Default value: Access: IRQSIG 0xFFFF0004 0x00000000 Read only
FAST INTERRUPT REQUEST (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR'ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks.
IRQEN
IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled or masked which does not create an IRQ exception. The IRQEN register cannot be used to disable an interrupt.
IRQEN Register
Name: Address: Default value: Access: IRQEN 0xFFFF0008 0x00000000 Read/write
FIQSIG
FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal, the corresponding bit in the FIQSIG is set, otherwise it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only.
IRQCLR
IRQCLR is a write-only register that allows the IRQEN register to clear in order to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write.
FIQSIG RegisterPrA
Name: Address: Default value: Access: FIQSIG 0xFFFF0104 0x00000000 Read only
IRQCLR Register
Name: Address: Default value: Access: IRQCLR 0xFFFF000C 0x00000000 Write only
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Preliminary Technical Data
FIQEN
FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or masked which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt.
ADUC7122
The 32-bit register dedicated to software interrupt is SWICFG described in Table 122. This MMR allows the control of a programmed source interrupt.
Table 122. SWICFG MMR Bit Designations
Bit 31 to 3 2 Description Reserved. Programmed Interrupt FIQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of FIQSTA and FIQSIG. Programmed Interrupt IRQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of IRQSTA and IRQSIG. Reserved.
FIQEN Register
Name: Address: Default value: Access: FIQEN 0xFFFF0108 0x00000000 Read/write
0 1
FIQCLR
FIQCLR is a write-only register that allows the FIQEN register to clear in order to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write.
Any interrupt signal must be active for at least the minimum interrupt latency time, to be detected by the interrupt controller and to be detected by the user in the IRQSTA/FIQSTA register.
PROGRAMMABLE PRIORITY PER INTERRUPT (IRQP0/IRQP1/IRQP2)
IRQ_SOURCE FIQ_SOURCE INTERNAL ARBITER LOGIC
POINTER TO FUNCTION (IRQVEC)
FIQCLR Register
Name: Address: Default value: Access: FIQCLR
INTERRUPT VECTOR
0xFFFF010C 0x00000000 Write only
BITS 31-23 UNUSED BITS 22-7 (IRQBASE) BITS 6-2 BITS 1-0 HIGHEST LSBs PRIORITY ACTIVE IRQ
Figure 36. Interrupt Structure
FIQSTA
FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine.
Vectored Interrupt Controller (VIC)
The ADUC7122 incorporates an enhanced interrupt control system or vectored interrupt controller. The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources. The vectored interrupt controller provides the following enhancements to the standard IRQ/FIQ interrupts: Vectored interrupts--allows a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and IRQVEC registers. IRQ/FIQ interrupts--can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is maximized, then it is possible to have 16 separate interrupt levels. Programmable interrupt priorities--using the IRQP0 to IRQP2 registers, an interrupt source can be assigned an interrupt priority level value between 1 and 8.
FIQSTA Register
Name: Address: Default value: Access: FIQSTA 0xFFFF0100 0x00000000 Read only
Programmed Interrupts
Because the programmed interrupts are not maskable, they are controlled by another register (SWICFG) that writes into both IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG registers at the same time.
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ADUC7122
VIC MMRs IRQBASE Register
The vector base register, IRQBASE, is used to point to the start address of memory used to store 32 pointer addresses. These pointer addresses are the addresses of the individual interrupt service routines. Name: Address: Default value: Access: IRQBASE 0xFFFF0014
Preliminary Technical Data
Priority Registers IRQP0 Register
Name: Address: Default value: Access: IRQP0 0xFFFF0020 0x00000000 Read and write
Table 125. IRQP0 MMR Bit Designations
0x00000000 Read and write
Bit 31:27 26:24 Description Always read as 0 Vector base address 23 22:20 19 18:16 15 14:12 11 10:8 7 6:4 3:0
Name Reserved T4PI Reserved T3PI Reserved T2PI Reserved T1PI Reserved T0PI Reserved SWINTP Reserved
Table 123. IRQBASE MMR Bit Designations
Bit 31:16 15:0 Type Read only R/W Initial Value Reserved 0
IRQVEC Register
The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register. Name: Address: Default value: Access: IRQVEC 0xFFFF001C 0x00000000 Read only
Description Reserved bit A priority level of 0 to 7 can be set for Timer 4. Reserved bit A priority level of 0 to 7 can be set for Timer 3. Reserved bit. A priority level of 0 to 7 can be set for Timer 2. Reserved bit. A priority level of 0 to 7 can be set for Timer 1. Reserved bit. A priority level of 0 to 7 can be set for Timer 0. Reserved bit A priority level of 0 to 7 can be set for the software interrupt source. Interrupt 0 cannot be prioritized.
IRQP1 Register
Name: Address: Default value: Access: IRQP1 0xFFFF0024 0x00000000 Read and write
Table 124. IRQVEC MMR Bit Designations
Bit 31:23 22:7 6:2 Type Read only R/W Read only Initial value 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority IRQ source. This is a value between 0 to 19 representing the possible interrupt sources. For example, if the highest currently active IRQ is Timer 1, then these bits are [01000]. Reserved bits.
1:0
Reserved
0
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Preliminary Technical Data
Table 126. IRQP1 MMR Bit Designations
Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7:3 2:0 Name Reserved I2C0MPI Reserved SPIPI Reserved UARTPI Reserved ADCPI Reserved Flash1PI Reserved Flash0PI Reserved PSMPI Description Reserved bit. A priority level of 0 to 7 can be set for I2C0 master. Reserved bit. A priority level of 0 to 7 can be set for SPI. Reserved bit. A priority level of 0 to 7 can be set for UART. Reserved bit. A priority level of 0 to 7 can be set for the ADC interrupt source. Reserved bit. A priority level of 0 to 7 can be set for the Flash Block 1 controller interrupt source. Reserved bit. A priority level of 0 to 7 can be set for the Flash Block 0 controller interrupt source. Reserved bits. A priority level of 0 to 7 can be set for the Power supply monitor interrupt source.
ADUC7122
IRQP3 Register
Name: Address: Default value: Access: IRQP3 0xFFFF002C 0x00000000 Read and write
Table 128. IRQP3 MMR Bit Designations
Bit 31:15 14:12 11 10:8 7 6:4 3 2:0 Name Reserved PLA1PI Reserved PLA0PI Reserved IRQ5PI Reserved IRQ4PI Description Reserved bit. A priority level of 0 to 7 can be set for PLA0. Reserved bit. A priority level of 0 to 7 can be set for PLA0. Reserved bit. A priority level of 0 to 7 can be set for IRQ5. Reserved bit. A priority level of 0 to 7 can be set for IRQ4.
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It contains two active bits. The first to enable nesting and prioritization of IRQ interrupts the other to enable nesting and prioritization of FIQ interrupts. If these bits are cleared, then FIQs and IRQs may still be used but it is not possible to nest IRQs or FIQs. Neither is it possible to set an interrupt source priority level. In this default state, an FIQ does have a higher priority than an IRQ. Name: Address: Default value: Access: IRQCONN 0xFFFF0030 0x00000000 Read and write
IRQP2 Register
Name: Address: Default value: Access: IRQP2 0xFFFF0028 0x00000000 Read and write
Table 127. . IRQP2 MMR Bit Designations
Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7 6:4 3 2:0 Name Reserved PWMPI Reserved IRQ3PI Reserved IRQ2PI Reserved IRQ1PI Reserved IRQ0PI Reserved I2C1SPI Reserved I2C1MPI Reserved I2C0SPI Description Reserved bit. A priority level of 0 to 7 can be set for PWM. Reserved bit. A priority level of 0 to 7 can be set for IRQ3. Reserved bit. A priority level of 0 to 7 can be set for IRQ2. Reserved bit. A priority level of 0 to 7 can be set for IRQ1. Reserved bit. A priority level of 0 to 7 can be set for IRQ0. Reserved bit. A priority level of 0 to 7 can be set for I2C1 slave. Reserved bit. A priority level of 0 to 7 can be set for I2C1 master. Reserved bit. A priority level of 0 to 7 can be set for I2C0 slave.
Table 129. IRQCONN MMR Bit Designations
Bit 31:2 1 Name Reserved ENFIQN Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Setting this bit to 1 enables nesting of IRQ interrupts. Clearing this bit means no nesting or prioritization of IRQs is allowed.
0
ENIRQN
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ADUC7122
IRQSTAN Register
If IRQCONN.0 is asserted and IRQVEC is read then one of these bits is asserted. The bit that asserts depend on the priority of the IRQ. If the IRQ is of Priority 0 then Bit 0 asserts, Priority 1 then Bit 1 asserts, and so forth. When a bit is set in this register, all interrupts of that priority and lower are blocked. To clear a bit in this register, all bits of a higher priority must be cleared first. It is only possible to clear one bit at a time. For example, if this register is set to 0x09 then writing 0xFF changes the register to 0x08, and writing 0xFF a second time changes the register to 0x00. Name: Address: Default value: Access: IRQSTAN 0xFFFF003C 0x00000000 Read and write
Preliminary Technical Data
FIQSTAN Register
If IRQCONN.1 is asserted and FIQVEC is read then one of these bits assert. The bit that asserts depends on the priority of the FIQ. If the FIQ is of Priority 0 then Bit 0 asserts, Priority 1 then Bit 1 asserts, and so forth. When a bit is set in this register all interrupts of that priority and lower are blocked. To clear a bit in this register all bits of a higher priority must be cleared first. It is only possible to clear one bit as a time. For example if this register is set to 0x09 then writing 0xFF changes the register to 0x08 and writing 0xFF a second time changes the register to 0x00. Name: Address: Default value: Access: FIQSTAN 0xFFFF013C 0x00000000 Read and write
Table 130. IRQSTAN MMR Bit Designations
Bit 31:8 7:0 Name Reserved Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit, means no nesting or prioritization of FIQs is allowed.
Table 132. FIQSTAN MMR Bit Designations
Bit 31:8 7:0 Name Reserved Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit, means no nesting or prioritization of FIQs is allowed.
FIQVEC Register
The FIQ interrupt vector register, FIQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. This register should only be read when an FIQ occurs and FIQ interrupt nesting has been enabled by setting Bit 1 of the IRQCONN register. Name: Address: Default value: Access: FIQVEC 0xFFFF011C 0x00000000 Read only
External Interrupts (IRQ0 to IRQ3)
The ADUC7122 provides up to four external interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. To enable the external interrupt source, first of all, the appropriate bit must be set in the FIQEN or IRQEN register. To select the required edge or level to trigger on, the IRQCONE register must be appropriately configured. To properly clear an edge based external IRQ interrupt, set the appropriate bit in the EDGELEVELCLR register.
IRQCONE Register
Name: Address: Default value: Access: IRQCONE 0xFFFF0034 0x00000000 Read and write
Table 131. FIQVEC MMR Bit Designations
Bit 31:23 22:7 6:2 Type Read only R/W Initial Value 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority FIQ source. This is a value between 0 to 19 represent the possible interrupt sources. For example, if the highest currently active FIQ is Timer 1, then these bits are 01000. Reserved bits.
1:0
Reserved
0
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ADUC7122
Table 133. IRQCONEMMR Bit Designations
Bit 31:12 11:10 Value 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 Name Reserved IRQ5SRC[1:0]
Preliminary Technical Data
Description These bits are reserved and should not be written to. External IRQ5 triggers on falling edge. External IRQ5 triggers on rising edge. External IRQ5 triggers on low level. External IRQ5 triggers on high level. External IRQ4 triggers on falling edge. External IRQ4 triggers on rising edge. External IRQ4 triggers on low level. External IRQ4 triggers on high level. External IRQ3 triggers on falling edge. External IRQ3 triggers on rising edge. External IRQ3 triggers on low level. External IRQ3 triggers on high level. External IRQ2 triggers on falling edge. External IRQ2 triggers on rising edge. External IRQ2 triggers on low level. External IRQ2 triggers on high level. External IRQ1 triggers on falling edge. External IRQ1 triggers on rising edge. External IRQ1 triggers on low level. External IRQ1 triggers on high level. External IRQ0 triggers on falling edge. External IRQ0 triggers on rising edge. External IRQ0 triggers on low level. External IRQ0 triggers on high level.
9:8
IRQ4SRC[1:0]
7:6
IRQ3SRC[1:0]
5:4
IRQ2SRC[1:0]
3:2
IRQ1SRC[1:0]
1:0
IRQ0SRC[1:0]
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ADUC7122
IRQCLRE Register
Name: Address: Default value: Access: IRQCLRE 0xFFFF0038 0x00000000 Read and write
ES 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001
Preliminary Technical Data
Table 135. Event Selection Numbers
Interrupt Number 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name RTOS timer (Timer0) GP Timer0 (Timer1) Wake-up timer (Timer2) Watchdog timer (Timer3) GP Timer4 (Timer4) Reserved Power supply monitor Undefined Flash Block 0 Flash Block 1 ADC UART SPI I2C0 master I2C0 slave I2C1 master I2C1 slave External IRQ0
Table 134. IRQCLRE MMR Bit Designations
Bit 31:20 19 Name Reserved IRQ3CLRI Description These bits are reserved and should not be written to. A 1 must be written to this bit in the IRQ3 interrupt service routine to clear an edge triggered IRQ3 interrupt. A 1 must be written to this bit in the IRQ2 interrupt service routine to clear an edge triggered IRQ2 interrupt. These bits are reserved and should not be written to. A 1 must be written to this bit in the IRQ1 interrupt service routine to clear an edge triggered IRQ1 interrupt. A 1 must be written to this bit in the IRQO interrupt service routine to clear an edge triggered IRQ0 interrupt. These bits are reserved and should not be written to.
18
IRQ2CLRI
17:15 14
Reserved IRQ1CLRI
TIMER0--LIFETIME TIMER
Timer0 is a general-purpose, 48-bit count up, or a 16-bit count up/down timer with a programmable prescaler. Timer0 is clocked from the core clock, with a prescaler of 1, 16, 256, or 32768. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Timer 0 can also be clocked from the undivided core clock, internal 32kHz oscillator or external 32kHz crystal. In 48-bit mode, Timer0 counts up from zero. The current counter value can be read from T0VAL0 and T0VAL1. In 16-bit mode, Timer0 can count up or count down. A 16-bit value can be written to T0LD that is loaded into the counter. The current counter value can be read from T0VAL0. Timer 0 has a capture register (T0CAP) that can be triggered by a selected IRQ's source initial assertion. Once triggered, the current timer value is copied to T0CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone. Timer0 reloads the value from T0LD either when TIMER0 overflows or immediately when T0CLRI is written.
13
IRQ0CLRI
12:0
Reserved
TIMERS
The ADUC7122 has five general purpose timers/counters. Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Timer4
The five timers in their normal mode of operation can be either free-running or periodic. In free-running mode, the counter decrements/increments from the maximum/minimum value until zero scale/full scale and starts again at the maximum /minimum value. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero scale/full scale and starts again at the value stored in the load register. The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time the value of the counter reaches zero if counting down, or full scale if counting up. An IRQ can be cleared by writing any value to clear register of the particular timer (TxICLR).
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Preliminary Technical Data
Timer0 interface consists of six MMRs, shown in Table 136.
Table 136. Timer0 Interface MMRs
Name T0LD Description 16-bit register that holds the 16-bit value loaded into the counter. Available only in 16-bit mode. 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Available only in 16-bit mode TOVAL0 is a 16 bit register that holds the 16 least significant bits (LSBs). T0VAL1 is a 32-bit register that holds the 32 most significant bits (MSBs). 8-bit register. Writing any value to this register clears the interrupt. Available only in 16-bit mode. Configuration MMR
ADUC7122
Table 138. Timer0 Control Register
Name T0CON Address 0xFFFF030C Default Value 0x00 Access R/W
The 17-bit MMR configures the mode of operation of Timer0.
Table 139. T0CON MMR Bit Designations
Bit 31:18 17 Value Description Reserved. Event select bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event select range, 0 to 16. The events are as described in the introduction to the timers. Reserved. Clock select. Internal 32 kHz oscillator. UCLK. External 32kHz crystal. HCLK. Count up. Available only in 16-bit mode. Set by user for timer 0 to count up. Cleared by user for timer 0 to count down (default). Timer0 enable bit. Set by user to enable Timer0. Cleared by user to disable Timer0 (default). Timer0 mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode (default). Reserved. Timer0 mode of operation. 16-bit operation (default). 48-bit operation. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. Source clock/32,768. Address 0xFFFF0300 Default Value 0x00 Access R/W
T0CAP
T0VAL0/T0VAL1
T0CLRI
16:12 11 10:9 00 01 10 11 8
T0CON
Table 137. Timer0 Value Register
Name T0VAL0/T0VAL1 Address 0xFFFF0304, 0xFFFF0308 Default Value 0x00, 0x00 Access R
T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold the 16 least significant bits and 32 most significant bits, respectively. T0VAL0 and T0VAL1 are read-only. In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0 and 32-bit T0VAL1 are used.
7
Timer0 Capture Register
Name T0CAP Address 0xFFFF0314 Default Value 0x00 Access R 6
This is a 16-bit register that holds the 16-bit value captured by an enabled IRQ event; only available in 16-bit mode.
5 4 0 1 3:0 0000 0100 1000 1111 Name T0LD
Timer0 Load Registers
T0LD is a 16-bit register that holds the 16-bit value that is loaded into the counter; available only in 16-bit mode.
Timer0 Clear Register
Name T0CLRI Address 0xFFFF0310 Default Value 0x00 Access W
This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer0.
Rev. PrA | Page 81 of 92
ADUC7122
TIMER1--GENERAL-PURPOSE TIMER
Timer1 is a 32-bit general-purpose timer, count down or count up, with a programmable prescaler. The prescaler source can be from the 32 kHz internal oscillator, the 32kHz external crystal, the core clock, or from the undivided PLL clock output. This source can be scaled by a factor of 1, 16, 256, or 32768. This gives a minimum resolution of 42 ns when operating at CD zero, the core is operating at 41.78 MHz, and with a prescaler of 1. The counter can be formatted as a standard 32-bit value or as Hours:Minutes:Seconds:Hundredths. Timer1 has a capture register (T1CAP) that can be triggered by a selected IRQ's source initial assertion. Once triggered, the current timer value is copied to T1CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. Timer1 interface consists of five MMRs as shown in the table below.
Table 140. Timer1 Interface Registers
Register T1LD T1VAL T1CAP T1ICLR T1CON Description 32-bit register. Holds 32-bit unsigned integers. This register is read only. 32-bit register. Holds 32-bit unsigned integers. 32-bit register; Holds 32-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer1 interrupt. Configuration MMR.
Preliminary Technical Data
Timer1 reloads the value from T1LD either when Timer1 overflows or immediately when T1ICLR is written.
Table 141. Timer1 Load Registers
Name Address Default Value Access T1LD 0xFFFF0320 0x00000 R/W T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter.
Table 142. Timer1 Clear Register
Name T1ICLR Address 0xFFFF032C Default Value 0x00 Access W
This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload) Timer1.
Table 143. Timer1 Value Register
Name T1VAL Address 0xFFFF0324 Default Value 0x0000 Access R
T1VAL is a 32-bit register that holds the current value of Timer1.
Table 144. Timer1 Capture Register
Name T1CAP Address 0xFFFF0330 Default Value 0x00 Access R
This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event.
Table 145. Timer1 Control Register.
Name T1CON Address 0xFFFF0328 Default Value 0x0000 Access R/W
Note that if the part is in a low power mode, and Timer1 is clocked from the GPIO or low power oscillator source, then Timer1 continues to operate.
This 32-bit MMR configures the mode of operation of Timer1.
Rev. PrA | Page 82 of 92
Preliminary Technical Data
Table 146. T1CON MMR Bit Designations
Bit 31:24 23 22:20 19 18 17 Value Description 8-bit postscaler. Enable write to postscaler. Reserved. Postscaler compare flag. T1 interrupt generation selection flag. Event select bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event select range, 0 to 16. The events are as described in the introduction to the timers. Clock Select. Internal 32 kHz oscillator (default). Core clock. UCLK. P0.6. Count up. Set by user for Timer1 to count up. Cleared by user for Timer1 to count down (default). Timer1 enable bit. Set by user to enable Timer1. Cleared by user to disable Timer1 (default). Timer1 mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:Min:Sec:Hundredths: 23 hours to 0 hours. Hr:Min:Sec:Hundredths: 255 hours to 0 hours. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. Source clock/32,768.
ADUC7122
16:12 11:9 000 001 010 011 8
7
6
5:4 00 01 10 11 3:0 0000 0100 1000 1111
Rev. PrA | Page 83 of 92
ADUC7122
TIMER2--WAKE-UP TIMER
Timer2 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from 1 of 4 clock sources, namely, the core clock (default selection), the internal 32.768 kHz oscillator, the external 32.768 kHz watch crystal, or the PLL undivided clock. The selected clock source can be scaled by a factor of 1, 16, 256, or 32768. The wake-up timer continues to run when the core clock is disabled. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via IRQEN[4]. The counter can be formatted as plain 32-bit value or as Hours:Minutes:Seconds:Hundredths. Timer2 reloads the value from T2LD either when Timer2 overflows or immediately when T2ICLR is written. The Timer2 interface consists of four MMRs, shown in the table below.
Table 147. Timer2 Interface Registers
Register T2LD T2VAL T2ICLR T2CON Description 32-bit register. Holds 32-bit unsigned integers. 32-bit register. Holds 32-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer2 interrupt. Configuration MMR. Name T2LD
Preliminary Technical Data
Table 148. Timer2 Load Registers
Address 0xFFFF0340 Default Value 0x00000 Access R/W
T2LD is a 32-bit register, which holds the 32 bit value that is loaded into the counter.
Table 149. Timer2 Clear Register
Name T2CLRI Address 0xFFFF034C Default Value 0x00 Access W
This 8-bit write-only MMR is written (with any value) by user code to refresh (reload) Timer2.
Table 150. Timer2 Value Register
Name T2VAL Address 0xFFFF0344 Default Value 0x0000 Access R
T2VAL is a 32-bit register that holds the current value of Timer2.
Table 151. Timer2 Control Register
Name T2CON Address 0xFFFF0348 Default Value 0x0000 Access R/W
This 32-bit MMR configures the mode of operation for Timer2.
Rev. PrA | Page 84 of 92
Preliminary Technical Data
Table 152. T2CON MMR Bit Designations
Bit 31:11 10:9 Value Description Reserved. Clock source select. Internal 32.768 kHz oscillator (default). Core clock. External 32.768 kHz watch crystal. UCLK. Count up. Set by user for Timer2 to count up. Cleared by user for Timer2 to count down (default). Timer2 enable bit. Set by user to enable Timer2. Cleared by user to disable Timer2 (default). Timer2 mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:Min:Sec:Hundredths. 23 hours to 0 hours. Hr:Min:Sec:Hundredths. 255 hours to 0 hours. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. (This setting should be used in conjunction with Timer2 Format 10 and Format 11.) Source clock/32,768.
ADUC7122
00 01 10 11 8
7
6
5:4 00 01 10 11 3:0 0000 0100 1000 1111
Rev. PrA | Page 85 of 92
ADUC7122
TIMER3--WATCHDOG TIMER
16-BIT LOAD
Preliminary Technical Data
Timer3 is automatically halted during JTAG debug access and only recommences counting once JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This can be disabled by setting Bit 0 in T3CON. It is recommended that the default value is used, that is, the watchdog timer continues to count during power-down.
06020-053
LOW POWER 32.768kHz
PRESCALER 1, 16, OR 256
16-BIT UP/DOWN COUNTER
WATCHDOG RESET TIMER3IRQ
Timer3 Interface
Timer3 interface consists of four MMRS as shown in the table below.
Table 153. Timer3 Interface Registers
Register T3CON T3LD T3VAL T3ICLR Description The configuration MMR. 6-bit registers (Bit 0 to Bit15); holds 16-bit unsigned integers. 6-bit registers (Bit 0 to Bit 15); holds 16-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode.
TIMER3 VALUE
Figure 37. Timer3 Block Diagram
Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a reset of the processor. Timer3 reloads the value from T3LD either when Timer3 overflows or immediately when T3ICLR is written.
Normal Mode
The Timer3 in normal mode is identical to Timer0 in 16-bit mode of operation, except for the clock source. The clock source is the 32.768 kHz oscillator and can be scaled by a factor of 1, 16, or 256. Timer3 also features a capture facility that allows capture of the current timer value if the Timer2 interrupt is enabled via IRQEN[5].
Table 154. Timer3 Load Register
Name T3LD Address 0xFFFF0360 Default Value 0x03D7 Access R/W
Watchdog Mode
Watchdog mode is entered by setting T3CON[5]. Timer3 decrements from the timeout value present in the T3LD register until 0. The maximum timeout is 512 seconds, using the maximum prescalar/256 and full scale in T3LD. User software should only configure a minimum timeout period of 30 milliseconds. This is to avoid any conflict with Flash/EE memory page erase cycles, requiring 20 ms to complete a single page erase cycle and kernel execution. If T3VAL reaches 0, a reset or an interrupt occurs, depending on T3CON[1]. To avoid a reset or an interrupt event, any value must be written to T3ICLR before T3VAL reaches zero. This reloads the counter with T3LD and begins a new timeout period. Once watchdog mode is entered, T3LD and T3CON are write protected. These two registers cannot be modified until a power-on reset event resets the watchdog timer. After any other reset event, the watchdog timer continues to count. The watchdog timer should be configured in the initial lines of user code to avoid an infinite loop of watchdog resets.
This 16-bit MMR holds the Timer3 reload value.
Table 155. Timer3 Value Register
Name T3VAL Address 0xFFFF0364 Default Value 0x03D7 Access R
This 16-bit, read-only MMR holds the currentTimer3 count value.
Table 156. Timer3 Clear Register
Name T3CLRI Address 0xFFFF036C Default Value 0x00 Access W
This 8-bit, write-only MMR is written (with any value) by user code to refresh (reload), Timer3 in watchdog mode to prevent a watchdog timer reset event.
Table 157. Timer3 Control Register
Name T3CON Address 0xFFFF0368 Default Value 0x00 Access R/W once only
The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 158.
Rev. PrA | Page 86 of 92
Preliminary Technical Data
Table 158. T3CON MMR Bit Designations
Bit 16:9 8 Value
ADUC7122
7
6
5
4
3:2 00 01 10 11 1
0
Description These bits are reserved and should be written as 0s by user code. Count up/down enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. Timer3 enable. Set by user code to enable Timer3. Cleared by user code to disable Timer3. Timer3 operating mode. Set by user code to configure Timer3 to operate in periodic mode. Cleared by user to configure Timer3 to operate in free-running mode. Watchdog timer mode enable. Set by user code to enable watchdog mode. Cleared by user code to disable watchdog mode. Secure clear bit. Set by user to use the secure clear option. Cleared by user to disable the secure clear option by default. Timer3 clock(32.768 kHz) prescaler. Source clock/1 (default). Reserved. Reserved. Reserved. Watchdog timer IRQ enable. Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by user code to disable the IRQ option. PD_OFF. Set by user code to stop Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR. Cleared by user code to enable Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T3ICLR to avoid a watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = X8 + X6 + X5 + X + 1.
Q 7 CLOCK D Q 6 D Q 5 D Q 4 D Q 3 D Q 2 D Q 1 D Q 0
06020-054
The value 0x00 should not be used as an initial seed due to the properties of the polynomial. The value 0x00 is always guaranteed to force an immediate reset. The value of the LFSR cannot be read; it must be tracked/generated in software. Example of a sequence: 1. 2. 3. 4. 5. Enter initial seed, 0xAA, in T3ICLR before starting Timer3 in watchdog mode. Enter 0xAA in T3ICLR; Timer3 is reloaded. Enter 0x37 in T3ICLR; Timer3 is reloaded. Enter 0x6E in T3ICLR; Timer3 is reloaded. Enter 0x66. 0xDC was expected; the watchdog resets the chip.
D
Figure 38. 8-Bit LFSR
The initial value or seed is written to T3ICLR before entering watchdog mode. After entering watchdog mode, a write to T3ICLR must match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens. If it fails to match the expected state, reset is immediately generated, even if the count has not yet expired.
Rev. PrA | Page 87 of 92
ADUC7122
TIMER4--GENERAL-PURPOSE TIMER
Timer4 is a 32-bit general-purpose timer, count down or count up, with a programmable prescalar. The prescalar source can be the 32kHz oscillator, the core clock or PLL undivided output. This source can be scaled by a factor of 1, 16, 256, or 32768. This gives a minimum resolution of 42 ns when operating at CD zero, the core is operating at 41.78 MHz, and with a prescalar of 1 ( ignoring external GPIO). The counter can be formatted as a standard 32-bit value or as Hours:Minutes:Seconds:Hundreths. Timer4 has a capture register (T4CAP), which can be triggered by a selected IRQ's source initial assertion. Once triggered, the current timer value is copied to T4CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. Timer4 interface consists of five MMRS. T4LD, T4VAL and T4CAP are 32-bit registers and hold 32-bit unsigned integers. T4VAL and T4CAP are read only. T4ICLR is an 8-bit register. Writing any value to this register clears the Timer1 interrupt.
Name T4LD
Preliminary Technical Data
Table 159. Timer4 Load Registers
Address 0xFFFF0380 Default Value 0x00000 Access R/W
T4LD is a 32-bit register, which holds the 32-bit value that is loaded into the counter.
Table 160. Timer4 Clear Register
Name T4CLRI Address 0xFFFF038C Default Value 0x00 Access W
This 8-bit, write only MMR is written (with any value) by user code to refresh (reload) Timer4.
Table 161. Timer4Value Register
Name Address Default Value Access T4VAL 0xFFFF0384 0x0000 R T4VAL is a 32-bit register that holds the current value of Timer4.
Table 162. Timer4 Capture Register
Name T4CAP Address 0xFFFF0390 Default Value 0x00 Access R
T4CON is the configuration MMR. Note that if the part is in a low power mode, and Timer 4 is clocked from the GPIO or oscillator source then, Timer 4 continues to operate. Timer4 reloads the value from T4LD either when Timer 4 overflows, or immediately when T4ICLR is written.
This is a 32-bit register that holds the 32-bit value captured by an enabled IRQ event.
Table 163. Timer4 Control Register
Name T4CON Address 0xFFFF0388 Default Value 0x0000 Access R/W
This 32-bit MMR configures the mode of operation of Timer4.
Rev. PrA | Page 88 of 92
Preliminary Technical Data
Table 164. T4CON MMR Bit Designations
Bit 31:18 17 Value Description Reserved. Set by user to 0. Event select bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Range, 0 to 31. The events are as described in the introduction to the timers. Clock select: 32.768 kHz oscillator. Core clock. UCLK. UCLK. Count up. Set by user for Timer4 to count up. Cleared by user for Timer4 to count down (default). Timer4 enable bit. Set by user to enable Timer4. Cleared by user to disable Timer4 (default). Timer4 mode. Set by user to operate in periodic mode. Cleared by user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr:Min:Sec:Hundredths: 23 hours to 0 hours. Hr:Min:Sec:Hundredths: 255 hours to 0 hours. Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. Source clock/32,768.
ADUC7122
16:12 11:9 000 001 010 011 8
7
6
5:4 00 01 10 11 3:0 0000 0100 1000 1111
Rev. PrA | Page 89 of 92
ADUC7122 OUTLINE DIMENSIONS
7.10 7.00 SQ 6.90
Preliminary Technical Data
A1 BALL CORNER
12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M
BALL A1 PAD CORNER 5.50 BSC SQ
0.50 BSC
TOP VIEW DETAIL A *1.40 MAX 0.15 MIN
BOTTOM VIEW
DETAIL A
*1.11 MAX
0.35 0.30 0.25 BALL DIAMETER
COPLANARITY 0.08 SEATING PLANE
*COMPLIANT WITH JEDEC STANDARDS MO-195-BD WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
Figure 39. 108-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-108-4 Dimensions shown in millimiters
ORDERING GUIDE
Model ADUC7122 Temperature Range -10C to +95C Package Description 108-Ball BGA package
Rev. PrA | Page 90 of 92
090408-A
Preliminary Technical Data NOTES
ADUC7122
Rev. PrA | Page 91 of 92
ADUC7122 NOTES
Preliminary Technical Data
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR08755-0-1/10(PrA)
Rev. PrA | Page 92 of 92

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